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    • 1. 发明授权
      US06307805B1 High performance semiconductor memory device with low power consumption 有权
    • High performance semiconductor memory device with low power consumption
    • 高性能半导体存储器件，功耗低
    • US06307805B1
    • 2001-10-23
    • US09745227
    • 2000-12-21
    • John E. Andersen , Terence B. Hook , Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
    • John E. Andersen , Terence B. Hook , Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
    • G11C700
    • G11C8/08 , G11C11/418 , H01L27/11
    • A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.
    • 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US06437623B1 Data retention registers 有权
    • Data retention registers
    • 数据保留寄存器
    • US06437623B1
    • 2002-08-20
    • US09782435
    • 2001-02-13
    • Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
    • Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
    • H03K3289
    • H03K3/0375 , G01R31/319 , H03K3/35625
    • A data retention system has master-slave latches for holding data in an active mode; a data retention latch for preserving data read from the master latch in a sleep mode, which is connected to the master latch in parallel with the slave latch; a first multiplexer for receiving data externally provided and feedback data from the data retention latch, and selectively outputting either the data externally provided or the feedback data to the master latch in response to a first control signal; and a second multiplexer for transferring output data of the master latch to the slave latch and the data retention latch in response to a second control signal, wherein power for the data retention latch remains turned on in the sleep mode, while power for the data retention system except for the data retention latch is turned off. The data retention latch may include gate transistors controlled by the second control signal and a data holding unit having transistors for holding data transferred through the gate transistors, wherein the gate transistors and the transistors in the data holding unit have a high-threshold voltage.
    • 数据保留系统具有用于保持活动模式下的数据的主从锁存器; 数据保持锁存器，用于在休眠模式下保存从主锁存器读取的数据，其与从锁存器并行连接到主锁存器; 第一多路复用器，用于接收外部提供的数据并从数据保持锁存器反馈数据，并且响应于第一控制信号选择性地输出外部提供的数据或反馈数据到主锁存器; 以及第二多路复用器，用于响应于第二控制信号将主锁存器的输出数据传送到从锁存器和数据保持锁存器，其中数据保持锁存器的电源在睡眠模式下保持导通，而数据保持功率 系统除了数据保持锁存器被关闭。 数据保持锁存器可以包括由第二控制信号控制的栅极晶体管和具有用于保持通过栅极晶体管传送的数据的晶体管的数据保持单元，其中数据保持单元中的栅极晶体管和晶体管具有高阈值电压。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US08561004B2 Ring power gating with distributed currents using non-linear contact placements 有权
    • Ring power gating with distributed currents using non-linear contact placements
    • 使用非线性触点放置的分布电流的环形电源门控
    • US08561004B2
    • 2013-10-15
    • US12758525
    • 2010-04-12
    • Stephen V. Kosonocky
    • Stephen V. Kosonocky
    • G06F17/50 , G06F9/455
    • H01L27/0207 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
    • A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.
    • 功率门包括沿着集成电路的至少一部分的一系列电触点和电耦合到集成电路上的电触点的一系列功率栅极晶体管，以形成例如集成电路外围的功率门边界。 沿着电源栅极边界的运行长度的至少一部分的电触点限定了基本上非线性的轮廓。 非线性轮廓提供增加的接触密度，其改善电触头之间的电流平衡和通过功率门的电流吞吐量。 非线性轮廓是具有中间偏移碰撞触点的正弦曲线或锯齿形图案。 沿着功率门边界的接触曲线可以包括线性和非线性轮廓。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      US20120126847A1 POWER SUPPLY MONITOR 有权
    • POWER SUPPLY MONITOR
    • 电源监控
    • US20120126847A1
    • 2012-05-24
    • US12950584
    • 2010-11-19
    • Stephen V. Kosonocky , Gregory K. Chen
    • Stephen V. Kosonocky , Gregory K. Chen
    • G01R31/40
    • G01R31/40
    • Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.
    • 通过逐周期监测环形振荡器的性能来测量电源变化和抖动。 通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。 计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。 基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07668035B2 Memory circuits with reduced leakage power and design structures for same 有权
    • Memory circuits with reduced leakage power and design structures for same
    • 具有减少泄漏功率的存储电路和相同的设计结构
    • US07668035B2
    • 2010-02-23
    • US12098764
    • 2008-04-07
    • Sam Gat-Shang Chu , Saiful Islam , Jae-Joon Kim , Stephen V. Kosonocky
    • Sam Gat-Shang Chu , Saiful Islam , Jae-Joon Kim , Stephen V. Kosonocky
    • G11C5/14
    • G11C7/18 , G11C7/12 , G11C11/413 , G11C2207/2227
    • A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.
    • 存储器电路包括全局读位线，全局读位线锁存器和多个子阵列，每个子阵列包括第一和第二本地读位线，第一和第二本地写位线以及第一和第二多个数组 分别与第一和第二本地读取位线以及第一和第二本地写入位线相互连接的存储器单元。 本地读位线与本地写位线分离。 本地多路复用块与第一和第二本地读位线互连，并且被配置为在断言SLEEP信号时对第一和第二本地读位线进行接地，并且选择性地将本地读位线互连到全局读位线 。 全局复用块与全局读位线互连，并且被配置为在断言SLEEP信号时将全局读位线保持在基本放电状态，并将全局读位线互连到全局读位线锁存器。 还包括所述类型的电路的设计结构。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US07057180B2 Detector for alpha particle or cosmic ray 失效
    • Detector for alpha particle or cosmic ray
    • α粒子或宇宙射线探测器
    • US07057180B2
    • 2006-06-06
    • US10604416
    • 2003-07-18
    • John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Stephen V. Kosonocky , Randy W. Mann , Jeffery H. Oppold , Norman J. Rohrer
    • John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Stephen V. Kosonocky , Randy W. Mann , Jeffery H. Oppold , Norman J. Rohrer
    • G01T1/24
    • G11C11/4125
    • A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.
    • 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。
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