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1. 发明申请

US20100153956A1 Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions 有权
标题翻译：基于执行指令配置核心功能的多核处理器和使用方法
公开(公告)号：US20100153956A1
公开(公告)日：2010-06-17
申请号：US12335696
申请日：2008-12-16
申请人： Louis B. Capps, JR. , Ronald E. Newhart , Thomas E. Cook , Robert H. Bell, JR. , Michael J. Shapiro
发明人： Louis B. Capps, JR. , Ronald E. Newhart , Thomas E. Cook , Robert H. Bell, JR. , Michael J. Shapiro
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/3802 , G06F9/5044 , G06F11/3024 , G06F11/3409 , G06F15/80 , G06F2209/501
摘要： A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
摘要翻译：具有多个异构处理单元的多处理器系统通过匹配处理单元的工作负载处理特性和指令集来调度在所选择的处理单元上执行的指令集。为了建立指令集的处理特性，通过在每个处理单元跟踪的一个或多个性能度量在多个处理单元中的每一个上执行均匀指令集，以确定哪个处理单元最有效地执行指令集。指令集工作负载处理特性被存储以用于调度指令集的后续执行。

2. 发明申请

US20090138220A1 Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开
标题翻译：基于多处理器目录的一致性协议的功率感知线路干预
公开(公告)号：US20090138220A1
公开(公告)日：2009-05-28
申请号：US11946551
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G01R21/02 , G06F12/08
CPC分类号： G06F12/0817 , Y02D10/13
摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

3. 发明申请

US20090138660A1 Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
标题翻译：多处理器侦听一致性协议的功率感知线路干预
公开(公告)号：US20090138660A1
公开(公告)日：2009-05-28
申请号：US11946249
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

4. 发明申请

US20100153700A1 Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions 有权
标题翻译：基于执行指令配置核心功能的多核处理器和使用方法
公开(公告)号：US20100153700A1
公开(公告)日：2010-06-17
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/22 , G06F9/318
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

5. 发明申请

US20120002812A1 DATA AND CONTROL ENCRYPTION 有权
标题翻译：数据和控制加密
公开(公告)号：US20120002812A1
公开(公告)日：2012-01-05
申请号：US12828080
申请日：2010-06-30
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Michael J. Shapiro
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Michael J. Shapiro
IPC分类号： H04L9/20 , H04L9/08 , H04K1/04 , H04L9/18
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译：设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据由密钥定义的加密顺序。加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。

6. 发明申请

US20090164812A1 Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效
标题翻译：动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能
公开(公告)号：US20090164812A1
公开(公告)日：2009-06-25
申请号：US11960163
申请日：2007-12-19
申请人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
发明人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译：提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。

7. 发明申请

US20090138682A1 Dynamic instruction execution based on transaction priority tagging 有权
标题翻译：基于事务优先级标记的动态指令执行
公开(公告)号：US20090138682A1
公开(公告)日：2009-05-28
申请号：US11946504
申请日：2007-11-28
申请人： Louis B. Capps, JR. , Robert H. Bell, JR.
发明人： Louis B. Capps, JR. , Robert H. Bell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3851 , G06F9/5011 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/885 , G06F2209/507 , Y02D10/22 , Y02D10/34
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将每个线程的分配优先级值作为标签存储在线程的指令中，基于分配给各个指令线程的标记的优先级值来分配来自系统调度的来自不同线程的标记指令。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

8. 发明申请

US20090138683A1 Dynamic instruction execution using distributed transaction priority registers 审中-公开
标题翻译：使用分布式事务优先级寄存器的动态指令执行
公开(公告)号：US20090138683A1
公开(公告)日：2009-05-28
申请号：US11946615
申请日：2007-11-28
申请人： Louis B. Capps, JR. , Robert H. Bell, JR.
发明人： Louis B. Capps, JR. , Robert H. Bell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/5011 , G06F2209/507 , Y02D10/22
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values in thread priority registers distributed throughout the computer system, instructions from different threads that are dispatched through the system are allocated system resources based on the priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将分配的优先级值存储在整个计算机系统中分配的线程优先级寄存器中，基于分配给各个指令线程的优先级值，分配来自系统调度的不同线程的指令被分配给系统资源。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

9. 发明申请

US20130111135A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

10. 发明申请

US20090186494A1 APPARATUS, SYSTEM, AND METHOD FOR A CONFIGURABLE BLADE CARD 有权
标题翻译：用于可配置刀片的设备，系统和方法
公开(公告)号：US20090186494A1
公开(公告)日：2009-07-23
申请号：US12016043
申请日：2008-01-17
申请人： Robert H. Bell, JR. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, JR. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： H01R12/00
CPC分类号： G06F13/409 , H05K7/1487
摘要： An apparatus, system, and method are disclosed for a configurable blade card. A base card is in physical and electrical communication with a blade connector. The blade connector is in physical and electrical communication with a blade enclosure connector. A secondary card is in physical and electrical communication with the base card to form a blade card. A coupler physically couples the base card and the secondary card. The base card and the secondary card are co-planar and compatible with a blade card form factor.
摘要翻译：公开了一种用于可配置的刀片卡的装置，系统和方法。基卡与刀片连接器物理和电气通信。刀片连接器与刀片机箱连接器物理和电气通信。辅助卡与基卡进行物理和电气通信以形成刀片卡。耦合器物理耦合基卡和辅助卡。基卡和辅助卡是共面的，与刀片卡形状兼容。

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