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    • 1. 发明授权
    • Auto-selecting holding current circuit
    • 自动选择保持电流电路
    • US08575901B2
    • 2013-11-05
    • US13410034
    • 2012-03-01
    • Lon-Kou ChangHsing-Fu LiuChang-Yu WuLi-Wei Yen
    • Lon-Kou ChangHsing-Fu LiuChang-Yu WuLi-Wei Yen
    • G05F1/40H05B41/36
    • H05B33/0806H05B39/044Y02B20/348
    • An auto-selecting holding current circuit is applicable to a converter. A primary side of the converter has a Triode for Alternating Current (TRIAC) and a bleeder circuit. The auto-selecting holding current circuit includes a first sensor module, a second sensor module and a reference voltage selecting circuit. The first sensor module detects an input current drop time or an input voltage drop time to output a sense signal. The second sensor module receives a current detector signal and outputs a critical current signal to detect a holding-current value range of the TRIAC. The reference voltage selecting circuit outputs a reference current signal to the bleeder circuit, and the reference current signal corresponds to a holding-current value of the TRIAC. Therefore, the bleeder circuit maintains normal operation of the TRIACs with different holding-current values.
    • 自动选择保持电流电路适用于转换器。 转换器的初级侧具有交流电三极管(TRIAC)和泄放电路。 所述自动选择保持电流电路包括第一传感器模块,第二传感器模块和参考电压选择电路。 第一传感器模块检测输入电流下降时间或输入电压下降时间以输出感测信号。 第二传感器模块接收电流检测器信号并输出​​临界电流信号以检测TRIAC的保持电流值范围。 参考电压选择电路向放大器电路输出参考电流信号,并且参考电流信号对应于TRIAC的保持电流值。 因此,泄放电路保持具有不同保持电流值的TRIAC的正常工作。
    • 2. 发明申请
    • AUTO-SELECTING HOLDING CURRENT CIRCUIT
    • 自动选择保持电流电路
    • US20130009616A1
    • 2013-01-10
    • US13410034
    • 2012-03-01
    • Lon-Kou ChangHsing-Fu LiuChang-Yu WuLi-Wei Yen
    • Lon-Kou ChangHsing-Fu LiuChang-Yu WuLi-Wei Yen
    • G05F1/455
    • H05B33/0806H05B39/044Y02B20/348
    • An auto-selecting holding current circuit is applicable to a converter. A primary side of the converter has a Triode for Alternating Current (TRIAC) and a bleeder circuit. The auto-selecting holding current circuit includes a first sensor module, a second sensor module and a reference voltage selecting circuit. The first sensor module detects an input current drop time or an input voltage drop time to output a sense signal. The second sensor module receives a current detector signal and outputs a critical current signal to detect a holding-current value range of the TRIAC. The reference voltage selecting circuit outputs a reference current signal to the bleeder circuit, and the reference current signal corresponds to a holding-current value of the TRIAC. Therefore, the bleeder circuit maintains normal operation of the TRIACs with different holding-current values.
    • 自动选择保持电流电路适用于转换器。 转换器的初级侧具有交流电三极管(TRIAC)和泄放电路。 所述自动选择保持电流电路包括第一传感器模块,第二传感器模块和参考电压选择电路。 第一传感器模块检测输入电流下降时间或输入电压下降时间以输出感测信号。 第二传感器模块接收电流检测器信号并输出​​临界电流信号以检测TRIAC的保持电流值范围。 参考电压选择电路向放大器电路输出参考电流信号,并且参考电流信号对应于TRIAC的保持电流值。 因此,泄放电路保持具有不同保持电流值的TRIAC的正常工作。
    • 3. 发明授权
    • Circuit regulator and synchronous timing pulse generation circuit thereof
    • 电路调节器及同步定时脉冲发生电路
    • US08422253B2
    • 2013-04-16
    • US12970029
    • 2010-12-16
    • Lon-Kou ChangChang-Yu WuHsing-Fu Liu
    • Lon-Kou ChangChang-Yu WuHsing-Fu Liu
    • H02M3/335
    • H02M1/08H02M3/33523
    • A circuit regulator is used to generate a pulse-width-modulation signal, so as to control a power to be selectively input or not input to a primary side of a switching power supply. The circuit regulator includes a synchronous timing pulse generation circuit, outputs a starting pulse after performing signal process of time delay, timing pulse regulation, and synchronization control on a pulse-width-modulation signal and a discharging time signal of a secondary side, and accordingly effectively controls a pulse starting time of the pulse-width-modulation signal. Therefore, the synchronous timing pulse generation circuit can be applied to the circuit regulator, so as to further effectively prevent an inductor current of the switching power supply from entering a Continuous Conduction Mode (CCM).
    • 电路调节器用于产生脉冲宽度调制信号,以便控制有选择地输入或不输入到开关电源的初级侧的功率。 电路调节器包括同步定时脉冲发生电路,对次级侧的脉宽调制信号和放电时间信号进行时间延迟,定时脉冲调整,同步控制等信号处理后的起始脉冲输出 有效地控制脉冲宽度调制信号的脉冲开始时间。 因此,可以将同步定时脉冲发生电路应用于电路调节器,以进一步有效地防止开关电源的电感电流进入连续导通模式(CCM)。
    • 4. 发明申请
    • ADAPTIVE BLEEDER CIRCUIT
    • 自适应电路
    • US20120188794A1
    • 2012-07-26
    • US13183007
    • 2011-07-14
    • Lon-Kou ChangChang-Yu WuLi-Wei Yen
    • Lon-Kou ChangChang-Yu WuLi-Wei Yen
    • H02M3/335
    • H02M3/33507H05B33/0809H05B33/0815H05B33/0845
    • An adaptive bleeder circuit is applicable to a power converter, in which the power converter has a transformer primary side and a transformer secondary side, and the power converter enables input power to be selectively input or not input to the transformer primary side through a pulse-width-modulated signal. The adaptive bleeder circuit includes a switched bleeder circuit, and the bleeder circuit switch dynamically adjusts a turn on/off ratio (or referred to as duty ratio) of the switch element according to the TRIAC holding current and the converter input current of an alternating current (AC) TRIAC. When the input current is less than the holding current, the bleeder circuit increases conduction time ratio of the pulse-width-modulated signal, such that the input current recovers to the holding current to maintain normal conduction of the AC TRIAC.
    • 自适应泄放电路适用于功率转换器,其中功率转换器具有变压器初级侧和变压器次级侧,并且功率转换器使得输入功率能够通过脉冲发生器选择性地输入或不输入到变压器初级侧, 宽度调制信号。 自适应泄放电路包括开关放电电路,泄放电路开关根据TRIAC保持电流和交流电流的转换器输入电流动态地调节开关元件的导通/截止比(或称为占空比) (AC)TRIAC。 当输入电流小于保持电流时,泄放电路增加了脉宽调制信号的导通时间比,使得输入电流恢复到保持电流以保持AC TRIAC的正常导通。
    • 5. 发明授权
    • Adaptive bleeder circuit
    • 自适应泄放电路
    • US08610375B2
    • 2013-12-17
    • US13183007
    • 2011-07-14
    • Lon-Kou ChangChang-Yu WuLi-Wei Yen
    • Lon-Kou ChangChang-Yu WuLi-Wei Yen
    • H05B37/02
    • H02M3/33507H05B33/0809H05B33/0815H05B33/0845
    • An adaptive bleeder circuit is applicable to a power converter, in which the power converter has a transformer primary side and a transformer secondary side, and the power converter enables input power to be selectively input or not input to the transformer primary side through a pulse-width-modulated signal. The adaptive bleeder circuit includes a switched bleeder circuit, and the bleeder circuit switch dynamically adjusts a turn on/off ratio (or referred to as duty ratio) of the switch element according to the TRIAC holding current and the converter input current of an alternating current (AC) TRIAC. When the input current is less than the holding current, the bleeder circuit increases conduction time ratio of the pulse-width-modulated signal, such that the input current recovers to the holding current to maintain normal conduction of the AC TRIAC.
    • 自适应泄放电路适用于功率转换器,其中功率转换器具有变压器初级侧和变压器次级侧,并且功率转换器使得输入功率能够通过脉冲发生器选择性地输入或不输入到变压器初级侧, 宽度调制信号。 自适应泄放电路包括开关放电电路,泄放电路开关根据TRIAC保持电流和交流电流的转换器输入电流动态地调节开关元件的导通/截止比(或称为占空比) (AC)TRIAC。 当输入电流小于保持电流时,泄放电路增加了脉宽调制信号的导通时间比,使得输入电流恢复到保持电流以保持AC TRIAC的正常导通。
    • 6. 发明授权
    • Device performance enhancement
    • 设备性能提升
    • US09142630B2
    • 2015-09-22
    • US13557479
    • 2012-07-25
    • Chang-Yu WuChih-Chiang ChangShang-Chih HsiehWei-Chih Hsieh
    • Chang-Yu WuChih-Chiang ChangShang-Chih HsiehWei-Chih Hsieh
    • H01L21/28H01L29/423H01L29/78
    • H01L29/4238H01L21/28123H01L29/78
    • Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
    • 除此之外,本文提供了用于增强器件(例如,晶体管)性能的一种或多种技术。 在一个实施例中,通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。 与非边缘区域相比,扩展虚拟区域中存在与半导体制造处理相关的限制。 因此,通过将栅极连接到有源区域来形成表现出增强的性能的器件,其中有源区域具有期望的形状,因为它包括在该区域的非边缘内。 例如,由于与半导体制造处理相关的限制,可以形成虚拟设备(例如,可能较不响应的)以包括扩展的虚拟区域,其中扩展的虚拟区域具有小于期望的轮廓。
    • 7. 发明授权
    • Scan flip-flop circuit having fast setup time
    • 具有快速建立时间的扫描触发器电路
    • US08667349B2
    • 2014-03-04
    • US13207494
    • 2011-08-11
    • Shang-Chih HsiehChih-Chiang ChangChang-Yu Wu
    • Shang-Chih HsiehChih-Chiang ChangChang-Yu Wu
    • G01R31/28
    • G01R31/318541
    • A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.
    • 扫描触发器电路包括用于向数据节点提供数据信号的输入级,其中输入级包括耦合到数据节点的晶体管器件的第一和第二堆叠。 第一堆栈在用于输入到数据节点的正常操作模式期间接收数据输入信号,并且第二堆栈在用于输入到数据节点的扫描测试模式期间接收扫描输入信号。 扫描触发器电路还包括直接耦合到数据节点的主锁存器,用于锁存来自输入级的数据信号并输出​​数据信号; 耦合到主锁存器的输出的从锁存器,用于锁存来自主锁存器的输出并输出该输出; 以及扫描和时钟控制逻辑模块。 扫描和时钟控制逻辑模块控制第一个堆栈,以在正常操作模式下将数据输入信号输入到数据节点。
    • 8. 发明申请
    • DEVICE PERFORMANCE ENHANCEMENT
    • 设备性能提升
    • US20140027821A1
    • 2014-01-30
    • US13557479
    • 2012-07-25
    • Chang-Yu WuChih-Chiang ChangShang-Chih HsiehWei-Chih Hsieh
    • Chang-Yu WuChih-Chiang ChangShang-Chih HsiehWei-Chih Hsieh
    • H01L21/28H01L29/78
    • H01L29/4238H01L21/28123H01L29/78
    • Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
    • 除此之外,本文提供了用于增强器件(例如,晶体管)性能的一种或多种技术。 在一个实施例中,通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。 与非边缘区域相比,扩展虚拟区域中存在与半导体制造处理相关的限制。 因此,通过将栅极连接到有源区域来形成表现出增强的性能的器件,其中有源区域具有期望的形状,因为它被包括在该区域的非边缘内。 例如,由于与半导体制造处理相关的限制,可以形成虚拟设备(例如,可能较不响应的)以包括扩展的虚拟区域,其中扩展的虚拟区域具有小于期望的轮廓。