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1. 发明授权

US09142630B2 Device performance enhancement 有权
标题翻译：设备性能提升
公开(公告)号：US09142630B2
公开(公告)日：2015-09-22
申请号：US13557479
申请日：2012-07-25
申请人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
发明人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
IPC分类号： H01L21/28 , H01L29/423 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28123 , H01L29/78
摘要： Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
摘要翻译：除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它包括在该区域的非边缘内。例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

2. 发明申请

US20140027821A1 DEVICE PERFORMANCE ENHANCEMENT 有权
标题翻译：设备性能提升
公开(公告)号：US20140027821A1
公开(公告)日：2014-01-30
申请号：US13557479
申请日：2012-07-25
申请人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
发明人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28123 , H01L29/78
摘要： Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
摘要翻译：除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它被包括在该区域的非边缘内。例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

3. 发明授权

US08514000B1 Meta-hardened flip-flop 有权
标题翻译：元硬化触发器
公开(公告)号：US08514000B1
公开(公告)日：2013-08-20
申请号：US13562539
申请日：2012-07-31
申请人： Wei-Chih Hsieh , Shang-Chih Hsieh , Chih-Chiang Chang
发明人： Wei-Chih Hsieh , Shang-Chih Hsieh , Chih-Chiang Chang
IPC分类号： H03K3/00
CPC分类号： H03K3/0375 , H03K3/356156
摘要： Some embodiments relate to a flip-flop having a data input terminal, a data output terminal and a clock terminal. The flip-flop includes a master latch, a slave latch, and an isolation element coupled between the master latch output and slave latch. The isolation element is arranged to isolate capacitive loading seen by the output of the master latch that comes from the slave latch. In some embodiments, the master latch includes one or more drive enhancement elements on its feedforward and feedback paths. The slave latch can also include one or more drive enhancement elements on its feedforward and feedback paths. These drive enhancement elements, particularly in combination with the isolation element, may help to reduce the setup and hold times and enhance meta-stability resistance of the flip-flop relative to conventional implementations. Other embodiments are also disclosed.
摘要翻译：一些实施例涉及具有数据输入端，数据输出端和时钟端的触发器。触发器包括主锁存器，从锁存器和耦合在主锁存器输出和从锁存器之间的隔离元件。隔离元件被布置成隔离来自从锁存器的主锁存器的输出所看到的电容性负载。在一些实施例中，主锁存器在其前馈和反馈路径上包括一个或多个驱动增强元件。从锁存器还可以在其前馈和反馈路径上包括一个或多个驱动增强元件。这些驱动增强元件，特别是与隔离元件组合，可以有助于减小建立和保持时间，并且增强触发器相对于传统实现方式的元稳定性。还公开了其他实施例。

4. 发明授权

US08667349B2 Scan flip-flop circuit having fast setup time 有权
标题翻译：具有快速建立时间的扫描触发器电路
公开(公告)号：US08667349B2
公开(公告)日：2014-03-04
申请号：US13207494
申请日：2011-08-11
申请人： Shang-Chih Hsieh , Chih-Chiang Chang , Chang-Yu Wu
发明人： Shang-Chih Hsieh , Chih-Chiang Chang , Chang-Yu Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.
摘要翻译：扫描触发器电路包括用于向数据节点提供数据信号的输入级，其中输入级包括耦合到数据节点的晶体管器件的第一和第二堆叠。第一堆栈在用于输入到数据节点的正常操作模式期间接收数据输入信号，并且第二堆栈在用于输入到数据节点的扫描测试模式期间接收扫描输入信号。扫描触发器电路还包括直接耦合到数据节点的主锁存器，用于锁存来自输入级的数据信号并输出数据信号; 耦合到主锁存器的输出的从锁存器，用于锁存来自主锁存器的输出并输出该输出; 以及扫描和时钟控制逻辑模块。扫描和时钟控制逻辑模块控制第一个堆栈，以在正常操作模式下将数据输入信号输入到数据节点。

5. 发明授权

US08552785B2 Pulse generator 有权
标题翻译：脉冲发生器
公开(公告)号：US08552785B2
公开(公告)日：2013-10-08
申请号：US13292124
申请日：2011-11-09
申请人： Ming-Zhang Kuo , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
发明人： Ming-Zhang Kuo , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
IPC分类号： G06F1/04
CPC分类号： H03K3/033
摘要： A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
摘要翻译：电路包括逻辑门和锁存器。逻辑门被配置为在第一输入处接收时钟信号。锁存器被布置在逻辑门的反馈回路中，并被配置为响应于由逻辑门输出的信号和时钟信号而将反馈信号输出到逻辑门的第二输入端。电路被配置为基于时钟信号的上升沿或下降沿中的一个输出脉冲信号。

6. 发明申请

US20130113537A1 PULSE GENERATOR 有权
标题翻译：脉冲发生器
公开(公告)号：US20130113537A1
公开(公告)日：2013-05-09
申请号：US13292124
申请日：2011-11-09
申请人： Ming-Zhang KUO , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
发明人： Ming-Zhang KUO , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
IPC分类号： H03K3/017 , H03K3/00 , H03H11/26
CPC分类号： H03K3/033
摘要： A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
摘要翻译：电路包括逻辑门和锁存器。逻辑门被配置为在第一输入处接收时钟信号。锁存器被布置在逻辑门的反馈回路中，并被配置为响应于由逻辑门输出的信号和时钟信号而将反馈信号输出到逻辑门的第二输入端。电路被配置为基于时钟信号的上升沿或下降沿中的一个输出脉冲信号。

7. 发明授权

US09304678B2 Switching method for electronic device 有权
标题翻译：电子设备切换方法
公开(公告)号：US09304678B2
公开(公告)日：2016-04-05
申请号：US13536645
申请日：2012-06-28
申请人： Chih-Chiang Chang , Chih-Hao Chen , Han-Chang Lin , Cho-Yi Lin
发明人： Chih-Chiang Chang , Chih-Hao Chen , Han-Chang Lin , Cho-Yi Lin
IPC分类号： G06F3/0488
CPC分类号： G06F3/04883
摘要： A switching method for an electronic device having sensing regions is mentioned. The switching method is configured to detect signals received by the electronic device, so as to switch the states of the electronic device. The switching method comprises receiving a first signal at a first moment and receiving a second signal at a second moment, wherein the first signal is generated by touching a first sensing region and the second signal is generated by touching a second sensing region; measuring a triggering duration and determining whether the triggering duration is consistent with a predetermined duration, when the first signal and the second signal are inputted simultaneously; switching the electronic device from a first state to a second state, if the triggering duration is consistent with the predetermined duration; and maintaining the electronic device in the first state, if the triggering duration is not consistent with the predetermined duration.
摘要翻译：提及具有感测区域的电子设备的切换方法。切换方法被配置为检测由电子设备接收的信号，以便切换电子设备的状态。切换方法包括在第一时刻接收第一信号并在第二时刻接收第二信号，其中通过触摸第一感测区域产生第一信号，并且通过触摸第二感测区域产生第二信号; 当同时输入第一信号和第二信号时，测量触发持续时间并确定触发持续时间是否与预定持续时间一致; 如果触发持续时间与预定持续时间一致，则将电子设备从第一状态切换到第二状态; 并且如果触发持续时间与预定持续时间不一致，则将电子设备维持在第一状态。

8. 发明授权

US09228328B2 Installation structure of countertop faucet 有权
标题翻译：台面龙头的安装结构
公开(公告)号：US09228328B2
公开(公告)日：2016-01-05
申请号：US13831855
申请日：2013-03-15
申请人： Ming-Hung Chen , Chih-Chiang Chang
发明人： Ming-Hung Chen , Chih-Chiang Chang
IPC分类号： E03C1/042 , E03C1/04
CPC分类号： E03C1/0401 , E03C1/0403 , E03C2001/0416 , Y10T137/598
摘要： An installation structure of countertop faucet includes a base having an insertion section extending through a mounting hole formed in a counter to engage a locking nut to be secured. The insertion section has a top end forming a receiving bore of which a circumferential wall forming two positioning holes communicating with the receiving bore. Each positioning hole receives therein a releasing module. The bottom of the base forms two water inlet passages communicating with the receiving bore and receiving stop valves therein and coupled to couplers for connection with water inlet tubes. A faucet has a joint section received in the receiving bore and having water guide tubes fit into the water inlet passages. The joint section forms two receiving apertures receiving therein positioning modules respectively engageable with the positioning holes to fix the faucet and being released by the releasing module to detach the faucet from the base.
摘要翻译：台面式水龙头的安装结构包括具有插入部分的基部，该插入部分延伸穿过形成在柜台中的安装孔，以与待固定的锁定螺母接合。插入部分具有形成容纳孔的顶端，周向壁形成与接收孔连通的两个定位孔。每个定位孔在其中容纳释放模块。基座的底部形成两个与接收孔连通并且在其中接收截止阀的水入口通道，并连接到用于与进水管连接的耦合器。水龙头具有容纳在接收孔中的接合部分，并且具有配合入水通道的导水管。接头部分形成两个容纳孔，其中定位模块分别可与定位孔接合以固定水龙头并由释放模块释放，从而将水龙头与基座分离。

9. 发明申请

US20140067348A1 ARRAY MODELING FOR ONE OR MORE ANALOG DEVICES 有权
标题翻译：一个或多个模拟器件的阵列建模
公开(公告)号：US20140067348A1
公开(公告)日：2014-03-06
申请号：US13596214
申请日：2012-08-28
申请人： Yang Chung-Chieh , Chih-Chiang Chang , Chung-Ting Lu
发明人： Yang Chung-Chieh , Chih-Chiang Chang , Chung-Ting Lu
IPC分类号： G06G7/48
CPC分类号： G06F17/5036 , G06F17/5063 , G06F17/5068
摘要： Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example.
摘要翻译：提供了一种或多种用于创建用于模拟设备建模的阵列模型的技术。在一个实施例中，阵列模型表示基于电路布局内的模拟设备的物理位置的模拟设备的模拟设备特性的平均值或标准偏差值，其中使用物理位置坐标物理坐标系映射到数组模型的坐标数组。以这种方式，可以使用阵列坐标系从阵列模型中获得平均值和标准偏差值。平均值和标准偏差值可用于对模拟装置进行建模，并因此对使用模拟装置的电路进行建模，以获得例如操作或行为的更准确或更现实的预测。

10. 发明授权

US08643141B2 Capacitor array layout arrangement for high matching methodology 有权
标题翻译：高匹配方法的电容阵列布局布置
公开(公告)号：US08643141B2
公开(公告)日：2014-02-04
申请号：US13602471
申请日：2012-09-04
申请人： Chung-Ting Lu , Chih-Chiang Chang
发明人： Chung-Ting Lu , Chih-Chiang Chang
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L27/016 , G06F17/5036 , H01L27/0805
摘要： Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed.
摘要翻译：一些实施例涉及布置在半导体衬底上的电容器阵列。电容器阵列包括布置成一系列行和列的单元电容器阵列。互连结构耦合阵列的单元电容器以建立多个电容器元件。各个电容器元件具有不同数量的单位电容器和不同的对应电容。在建立多个电容器元件时，互连结构将平行于半导体衬底上的基本相同的子阵列中的阵列的单元电容器耦合。还公开了其它方法和装置。

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