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1. 发明授权

US6051493A Process for protecting bonded components from plating shorts 失效
标题翻译：保护接合部件免受镀层短路的工艺
公开(公告)号：US6051493A
公开(公告)日：2000-04-18
申请号：US323410
申请日：1994-10-14
申请人： Lisa A. Tarte , Wayne L. Bonde , Paul G. Carey , Robert J. Contolini , Anthony M. McCarthy
发明人： Lisa A. Tarte , Wayne L. Bonde , Paul G. Carey , Robert J. Contolini , Anthony M. McCarthy
IPC分类号： H01L21/60 , H01L21/44
CPC分类号： H01L24/80 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14
摘要： A method which protects the region between a component and the substrate onto which the components is bonded using an electrically insulating fillet of photoresist. The fillet protects the regions from subsequent plating with metal and therefore shorting the plated conductors which run down the sides of the component and onto the substrate.
摘要翻译：使用光刻胶的电绝缘圆角来保护组件与组件与基板之间的区域的方法。圆角保护区域免受金属的后续镀覆，从而使从元器件的侧面向下延伸到衬底上的电镀导体短路。

2. 发明授权

US6139716A Submicron patterned metal hole etching 失效
标题翻译：亚微米图案金属孔蚀刻
公开(公告)号：US6139716A
公开(公告)日：2000-10-31
申请号：US315387
申请日：1999-05-18
申请人： Anthony M. McCarthy , Robert J. Contolini , Vladimir Liberman , Jeffrey Morse
发明人： Anthony M. McCarthy , Robert J. Contolini , Vladimir Liberman , Jeffrey Morse
IPC分类号： C25F3/12
CPC分类号： C25F3/12
摘要： A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.
摘要翻译：借助于润湿剂，使用电化学蚀刻在薄金属层中蚀刻亚微米图案化孔的湿法化学方法。在此过程中，待处理的待蚀刻晶片在将经处理的晶片插入电化学蚀刻装置之前，浸入润湿剂（如甲醇）中几秒钟，晶片在转移过程中保持水平，以保持甲醇膜覆盖图案区域。电化学蚀刻装置包括密封晶片边缘的管，防止甲醇损失。将由4:1水：硫酸盐组成的电解液倒入管中，并且电解质代替图案化孔中的润湿剂。将工作电极连接到晶片的金属层上，其中参考电极和对置电极插入电解质中，所有电极连接到恒电位仪。对电极上的单个脉冲，例如+10.2伏特的100ms脉冲，用于激发电化学电路并进行蚀刻。该方法对金属层中的图案化孔进行均匀蚀刻，例如晶片的铬和钼，而不会对图案化掩模产生不利影响。

3. 发明授权

US06649977B1 Silicon on insulator self-aligned transistors 失效
标题翻译：硅绝缘体自对准晶体管
公开(公告)号：US06649977B1
公开(公告)日：2003-11-18
申请号：US08526339
申请日：1995-09-11
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78621
摘要： A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.
摘要翻译：一种制造薄膜单晶硅绝缘体（SOI）自对准晶体管的方法。硅衬底的标准处理用于制造晶体管。通过蚀刻多晶硅栅极材料引入的源极和栅极之间的物理空间以及漏极和栅极被用于提供允许晶体管正常执行的连接注入（桥）。在硅衬底处理完成之后，将硅晶片接合到绝缘体（玻璃）衬底，并且去除硅衬底，留下绝缘体（玻璃）衬底上的晶体管。通过该方法制造的晶体管可以用于例如平板显示器等。

4. 发明授权

US06346461B1 Electroless epitaxial etching for semiconductor applications 失效
标题翻译：半导体应用的无电镀外延蚀刻
公开(公告)号：US06346461B1
公开(公告)日：2002-02-12
申请号：US09570888
申请日：2000-05-15
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L2120
CPC分类号： H01L21/2007 , H01L21/76251
摘要： A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.
摘要翻译：一种使用无电蚀刻制造绝缘体上薄膜单晶硅的方法，用于在外延硅衬底上实现有效的蚀刻停止。在标准制造设备中的外延硅晶片上制备微电路和器件。晶片结合到保持基板上。使用化学蚀刻去除硅体积，留下保留在保持基板上的外延层中所含的电路。然后执行光刻操作以限定用于对电路进行电接入的街道和接线焊盘区域。

5. 发明授权

US5488012A Silicon on insulator with active buried regions 失效
标题翻译：硅绝缘体上有主动埋藏区域
公开(公告)号：US5488012A
公开(公告)日：1996-01-30
申请号：US137412
申请日：1993-10-18
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L21/20 , H01L21/306 , H01L21/74 , H01L21/762 , H01L21/76
CPC分类号： H01L21/74 , H01L21/2007 , H01L21/30608 , H01L21/743 , H01L21/76251 , Y10S148/012 , Y10S148/15 , Y10S438/97
摘要： A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.
摘要翻译：一种用于在绝缘体上硅（SOI）器件中形成图案化掩埋部件的方法，例如集电器，源极和漏极。该方法通过外延生长在硅衬底上以薄硅层结束的合适顺序的单个或多个蚀刻停止层，掩蔽硅，使得期望的图案被暴露，将掺杂剂引入并在薄硅层中激活形成掺杂区域。然后，将硅层粘合到绝缘体基板上，并且去除硅衬底。该方法还涉及在用于埋藏式收集器的薄硅层中形成电接触区域。

6. 发明授权

US5663078A Method for fabricating transistors using crystalline silicon devices on glass 失效
标题翻译：在玻璃上制造晶体硅晶体管的方法
公开(公告)号：US5663078A
公开(公告)日：1997-09-02
申请号：US373716
申请日：1995-01-17
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L21/20 , H01L21/306 , H01L21/331 , H01L21/336 , H01L21/762 , H01L29/73 , H01L29/786 , H01L21/786
CPC分类号： H01L29/66265 , H01L21/2007 , H01L21/30604 , H01L21/76264 , H01L29/42392 , H01L29/66772 , H01L29/7317 , H01L29/78633 , H01L29/78645 , H01L29/78648 , H01L29/78654 , Y10S438/97
摘要： A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.
摘要翻译：一种使用玻璃上的单晶硅器件制造晶体管的方法。该方法克服了在高电压接合期间可能对器件造成的潜在损害，并且采用可以作为晶体管的一部分并入的金属层。这样做是这样的：当硅晶片或衬底与玻璃衬底的接合被执行时，电压和电流通过不会制造晶体管的区域。在去除硅衬底之后，可以沉积另外的金属以形成电接触或向器件添加功能。通过这种方法，可以形成单个和全部四极设备。

7. 发明授权

US5760443A Silicon on insulator with active buried regions 失效
公开(公告)号：US5760443A
公开(公告)日：1998-06-02
申请号：US547080
申请日：1995-10-23
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L21/20 , H01L21/306 , H01L21/74 , H01L21/762 , H01L21/76
CPC分类号： H01L21/74 , H01L21/2007 , H01L21/30608 , H01L21/743 , H01L21/76251 , Y10S148/012 , Y10S148/15 , Y10S438/97
摘要： A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.

8. 发明授权

US5674758A Silicon on insulator achieved using electrochemical etching 失效
标题翻译：使用电化学蚀刻实现绝缘体上硅
公开(公告)号：US5674758A
公开(公告)日：1997-10-07
申请号：US484062
申请日：1995-06-06
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L21/20 , H01L21/84 , H01L21/3063
CPC分类号： H01L21/265 , Y10S148/012 , Y10S148/135 , Y10S438/924 , Y10S438/977 , Y10S438/98
摘要： Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.
摘要翻译：在完成电路制造之后转移块状晶体硅晶片，以在几乎任何支撑物上形成晶体电路薄膜，例如金属，半导体，塑料，聚合物，玻璃，木材和纸张。特别地，该技术适合于形成绝缘体上硅（SOI）晶片，由此，由于硅衬底的移除，所形成的器件和电路在转移之后表现出优异的性能。传统工艺对常规硅制造的成本并不显着。不需要外延，剥离，释放或掩埋氧化物层来执行将单个或多个晶片转移到支撑构件上。转印过程可以在50℃或更低的温度下进行，允许电路周围的透明度，并且不需要后转印图案化。因此，该技术为高亮度，高分辨率视频速度彩色显示器，减薄厚度增加灵活性智能卡，超薄支持元件上的柔性电子元件，粘合电子产品，触摸屏幕，开发了集成电路设备的新途径电子产品，需要低重量材料的物品，智能卡，加密系统的智能钥匙，玩具，大面积电路，柔性支架和其他应用。增加的过程灵活性还允许一种便宜的技术，以增加市场驱动的技术（如微处理器）的电路速度。

9. 发明授权

US5414276A Transistors using crystalline silicon devices on glass 失效
标题翻译：晶体管在玻璃上使用晶体硅器件
公开(公告)号：US5414276A
公开(公告)日：1995-05-09
申请号：US137402
申请日：1993-10-18
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： H01L21/20 , H01L21/306 , H01L21/331 , H01L21/336 , H01L21/762 , H01L29/73 , H01L29/786 , H01L29/04 , H01L29/78
CPC分类号： H01L29/66265 , H01L21/2007 , H01L21/30604 , H01L21/76264 , H01L29/42392 , H01L29/66772 , H01L29/7317 , H01L29/78633 , H01L29/78645 , H01L29/78648 , H01L29/78654 , Y10S438/97
摘要： A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.
摘要翻译：一种使用玻璃上的单晶硅器件制造晶体管的方法。该方法克服了在高电压接合期间可能对器件造成的潜在损害，并且采用可以作为晶体管的一部分并入的金属层。这样做是这样的：当硅晶片或衬底与玻璃衬底的接合被执行时，电压和电流通过不会制造晶体管的区域。在去除硅衬底之后，可以沉积另外的金属以形成电接触或向器件添加功能。通过这种方法，可以形成单个和全部四极设备。

10. 发明授权

US5399231A Method of forming crystalline silicon devices on glass 失效
标题翻译：在玻璃上形成晶体硅器件的方法
公开(公告)号：US5399231A
公开(公告)日：1995-03-21
申请号：US137411
申请日：1993-10-18
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： G02F1/1362 , H01L21/20 , H01L21/306 , B44C1/22 , C03C15/00
CPC分类号： H01L21/2007 , G02F1/13454 , H01L27/1214 , H01L27/1266 , Y10S148/035
摘要： A method for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics.
摘要翻译：一种在硅衬底上制造单晶硅微电子元件并将其转移到玻璃衬底的方法。这通过利用用于制造体硅的电子电路和器件的部件的常规硅处理技术来实现，其中在常规处理之前制备具有外延层的体硅表面。将硅衬底接合到玻璃衬底上，并移除体硅，使组分在玻璃衬底表面上完好无损。随后的标准处理完成了器件和电路制造。本发明在需要透明或绝缘基材，特别是显示器制造的应用中是有用的。其他应用包括传感器，执行器，光电子，辐射硬电子和高温电子。

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