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    • 1. 发明申请
    • TOUCH PANEL AND REPAIRING METHOD THEREOF
    • 触摸面板及其修复方法
    • US20120081300A1
    • 2012-04-05
    • US12970969
    • 2010-12-17
    • Lih-Hsiung ChanShine-Kai TsengChin-Yueh LiaoHung-Wen Chou
    • Lih-Hsiung ChanShine-Kai TsengChin-Yueh LiaoHung-Wen Chou
    • G06F3/041H01R43/00
    • G06F3/044G06F3/047G06F2203/04103G06F2203/04111G06F2203/04112Y10T29/49117
    • A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.
    • 提供了包括基板,多个第一和第二感测系列以及多个导电修复图案层的触摸面板。 第一感测系列设置在基板上并沿着第一方向延伸。 第一感测系列中的每一个包括多个第一感测焊盘和第一桥接线,并且第一桥接线串联连接两个相邻的第一感测焊盘。 第二感测系列设置在基板上并沿着第二方向延伸。 第二感测系列中的每一个包括多个第二感测焊盘和第二桥接线,并且第二桥接线串联地连接两个相邻的第二感测焊盘。 电浮动的每个导电修复图案层位于第一和第二感测系列的交叉区域周围。 在修复过程完成后,两个相邻的传感垫通过导电修复图案层连接。
    • 2. 发明申请
    • THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
    • 薄膜晶体管阵列基板及其制造方法
    • US20100320466A1
    • 2010-12-23
    • US12560428
    • 2009-09-16
    • Chien-Hung ChenLih-Hsiung ChanChin-Yueh LiaoHsien-Kai Tseng
    • Chien-Hung ChenLih-Hsiung ChanChin-Yueh LiaoHsien-Kai Tseng
    • H01L33/00H01L21/28
    • H01L27/1288H01L27/1214H01L27/124H01L27/1248
    • A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.
    • 提供薄膜晶体管阵列基板及其制造方法。 在制造方法中,在基板上形成包括多条扫描线的第一图案化导电层和与扫描线连接的多个栅极。 然后在衬底上形成具有多个开口的图案化栅极绝缘层,以覆盖第一图案化导电层的至少一部分,并且在开口中形成多个电介质图案。 在图案化的栅极绝缘层上形成多个半导体图案。 在半导体图案,图案化栅极绝缘层和电介质图案上形成第二图案化导电层。 在半导体图案,图案化栅绝缘层和电介质图案上形成钝化层。 在钝化层上形成多个像素电极。
    • 3. 发明授权
    • Thin film transistor array substrate and manufacturing method thereof
    • 薄膜晶体管阵列基板及其制造方法
    • US08314423B2
    • 2012-11-20
    • US12560428
    • 2009-09-16
    • Chien-Hung ChenLih-Hsiung ChanChin-Yueh LiaoHsien-Kai Tseng
    • Chien-Hung ChenLih-Hsiung ChanChin-Yueh LiaoHsien-Kai Tseng
    • H01L29/786
    • H01L27/1288H01L27/1214H01L27/124H01L27/1248
    • A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.
    • 提供薄膜晶体管阵列基板及其制造方法。 在制造方法中,在基板上形成包括多条扫描线的第一图案化导电层和与扫描线连接的多个栅极。 然后在衬底上形成具有多个开口的图案化栅极绝缘层,以覆盖第一图案化导电层的至少一部分,并且在开口中形成多个电介质图案。 在图案化的栅极绝缘层上形成多个半导体图案。 在半导体图案,图案化栅极绝缘层和电介质图案上形成第二图案化导电层。 在半导体图案,图案化栅绝缘层和电介质图案上形成钝化层。 在钝化层上形成多个像素电极。
    • 5. 发明申请
    • Electrophoretic deposition method for a field emission device
    • 场致发射器件的电泳沉积方法
    • US20060249388A1
    • 2006-11-09
    • US11121712
    • 2005-05-04
    • Yu-Yang ChangLih-Hsiung ChanKwan-Sin Ho
    • Yu-Yang ChangLih-Hsiung ChanKwan-Sin Ho
    • C25B7/00
    • C25D13/02C25D13/12H01J9/025
    • The invention provides an electrophoretic deposition method of CNTs for a field emission device. It uses a triode structure having gates and a proper arrangement of applied voltages to improve the selectivity of the conventional EPD method. The electric field around the gates repels the charged or polarized nanostructure suspension in the electrophoresis bath and prevents the charged or polarized nanostructure materials from depositing in the neighborhood of the gates. Therefore, the nanostructure materials are selectively deposited on the cathode. An electrical short circuit between the gates and the cathodes can be avoided. It does not require a masked sacrificial layer, and therefore keeps the manufacturing process simple and the cost down.
    • 本发明提供了一种用于场致发射器件的CNT的电泳沉积方法。 它使用具有栅极的三极管结构和施加的电压的适当布置以提高常规EPD方法的选择性。 栅极周围的电场排斥电泳槽中带电或极化的纳米结构悬浮液,并防止带电或极化的纳米结构材料沉积在栅极附近。 因此,纳米结构材料被选择性地沉积在阴极上。 可以避免栅极和阴极之间的电短路。 它不需要掩模的牺牲层,因此使制造工艺简单和成本降低。