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1. 发明申请

US20100320466A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20100320466A1
公开(公告)日：2010-12-23
申请号：US12560428
申请日：2009-09-16
申请人： Chien-Hung Chen , Lih-Hsiung Chan , Chin-Yueh Liao , Hsien-Kai Tseng
发明人： Chien-Hung Chen , Lih-Hsiung Chan , Chin-Yueh Liao , Hsien-Kai Tseng
IPC分类号： H01L33/00 , H01L21/28
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1248
摘要： A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.
摘要翻译：提供薄膜晶体管阵列基板及其制造方法。在制造方法中，在基板上形成包括多条扫描线的第一图案化导电层和与扫描线连接的多个栅极。然后在衬底上形成具有多个开口的图案化栅极绝缘层，以覆盖第一图案化导电层的至少一部分，并且在开口中形成多个电介质图案。在图案化的栅极绝缘层上形成多个半导体图案。在半导体图案，图案化栅极绝缘层和电介质图案上形成第二图案化导电层。在半导体图案，图案化栅绝缘层和电介质图案上形成钝化层。在钝化层上形成多个像素电极。

2. 发明授权

US08314423B2 Thin film transistor array substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US08314423B2
公开(公告)日：2012-11-20
申请号：US12560428
申请日：2009-09-16
申请人： Chien-Hung Chen , Lih-Hsiung Chan , Chin-Yueh Liao , Hsien-Kai Tseng
发明人： Chien-Hung Chen , Lih-Hsiung Chan , Chin-Yueh Liao , Hsien-Kai Tseng
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1248
摘要： A thin film transistor array substrate and a manufacturing method thereof are provided. In the manufacturing method, a first patterned conductive layer including a plurality of scan lines and a plurality of gates connected with the scan lines is formed on a substrate. A patterned gate insulating layer having a plurality of openings is then formed on the substrate to cover at least a portion of the first patterned conductive layer, and a plurality of dielectric patterns are formed in the openings. A plurality of semiconductor patterns are formed on the patterned gate insulating layer. A second patterned conductive layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A passivation layer is formed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns. A plurality of pixel electrodes are formed on the passivation layer.
摘要翻译：提供薄膜晶体管阵列基板及其制造方法。在制造方法中，在基板上形成包括多条扫描线的第一图案化导电层和与扫描线连接的多个栅极。然后在衬底上形成具有多个开口的图案化栅极绝缘层，以覆盖第一图案化导电层的至少一部分，并且在开口中形成多个电介质图案。在图案化的栅极绝缘层上形成多个半导体图案。在半导体图案，图案化栅极绝缘层和电介质图案上形成第二图案化导电层。在半导体图案，图案化栅绝缘层和电介质图案上形成钝化层。在钝化层上形成多个像素电极。

3. 发明申请

US20120081300A1 TOUCH PANEL AND REPAIRING METHOD THEREOF 审中-公开
标题翻译：触摸面板及其修复方法
公开(公告)号：US20120081300A1
公开(公告)日：2012-04-05
申请号：US12970969
申请日：2010-12-17
申请人： Lih-Hsiung Chan , Shine-Kai Tseng , Chin-Yueh Liao , Hung-Wen Chou
发明人： Lih-Hsiung Chan , Shine-Kai Tseng , Chin-Yueh Liao , Hung-Wen Chou
IPC分类号： G06F3/041 , H01R43/00
CPC分类号： G06F3/044 , G06F3/047 , G06F2203/04103 , G06F2203/04111 , G06F2203/04112 , Y10T29/49117
摘要： A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.
摘要翻译：提供了包括基板，多个第一和第二感测系列以及多个导电修复图案层的触摸面板。第一感测系列设置在基板上并沿着第一方向延伸。第一感测系列中的每一个包括多个第一感测焊盘和第一桥接线，并且第一桥接线串联连接两个相邻的第一感测焊盘。第二感测系列设置在基板上并沿着第二方向延伸。第二感测系列中的每一个包括多个第二感测焊盘和第二桥接线，并且第二桥接线串联地连接两个相邻的第二感测焊盘。电浮动的每个导电修复图案层位于第一和第二感测系列的交叉区域周围。在修复过程完成后，两个相邻的传感垫通过导电修复图案层连接。

4. 发明申请

US20090242883A1 Thin film transistor, active array substrate and method for manufacturing the same 审中-公开
标题翻译：薄膜晶体管，有源阵列基板及其制造方法
公开(公告)号：US20090242883A1
公开(公告)日：2009-10-01
申请号：US12149858
申请日：2008-05-09
申请人： Han-Tu Lin , Chih-Chun Yang , Chin-Yueh Liao , Chien-Hung Chen
发明人： Han-Tu Lin , Chih-Chun Yang , Chin-Yueh Liao , Chien-Hung Chen
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L29/42384 , H01L27/1218 , H01L27/124 , H01L29/66765 , H01L29/78603
摘要： A thin film transistor, an active array substrate having the same and methods for manufacturing the same are provided. The thin film transistor includes a base having a concave; a gate disposed in the concave; a gate insulator covering the gate and a portion of the gate insulator is in the concave; a channel layer disposed on the gate insulator; and a source and a drain are disposed on the channel layer and located in response to two sides of the gate.
摘要翻译：提供薄膜晶体管，具有该薄膜晶体管的有源阵列基板及其制造方法。薄膜晶体管包括具有凹面的基底; 设置在凹面中的门; 覆盖栅极的栅极绝缘体和栅极绝缘体的一部分在凹部中; 设置在栅极绝缘体上的沟道层; 并且源极和漏极设置在沟道层上并且响应于栅极的两侧而定位。

5. 发明授权

US07897442B2 Method for fabricating pixel structure 有权
标题翻译：制造像素结构的方法
公开(公告)号：US07897442B2
公开(公告)日：2011-03-01
申请号：US12105278
申请日：2008-04-18
申请人： Ta-Wen Liao , Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Chin-Yueh Liao , Chia-Chi Tsai
发明人： Ta-Wen Liao , Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Chin-Yueh Liao , Chia-Chi Tsai
IPC分类号： H01L21/00
CPC分类号： G02F1/136227 , G02F1/13439
摘要： A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain.
摘要翻译：公开了一种用于制造像素结构的方法。提供基板。第一导电层形成在衬底上，并且暴露第一导电层的一部分的第一阴影掩模设置在第一导电层上。激光用于照射第一导电层以去除第一导电层的一部分并形成栅极。栅极电介质层形成在衬底上以覆盖栅极。沟道层形成在栅极上的栅极电介质层上。源极和漏极形成在沟道层上并且分别在栅极的两侧上方。形成图案化的钝化层以覆盖沟道层并露出漏极。形成电极材料层以覆盖图案化的钝化层和暴露的漏极。

6. 发明申请

US20110070671A1 FABRICATING METHOD OF A PIXEL UNIT 审中-公开
标题翻译：像素单元的制作方法
公开(公告)号：US20110070671A1
公开(公告)日：2011-03-24
申请号：US12953472
申请日：2010-11-24
申请人： Chin-Yueh Liao , Chih-Chun Yang , Chih-Hung Shih , Shine-Kai Tseng
发明人： Chin-Yueh Liao , Chih-Chun Yang , Chih-Hung Shih , Shine-Kai Tseng
IPC分类号： H01L33/36
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof. A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.
摘要翻译：提供了一种用于制造像素单元的方法。在基板上形成TFT。保护层和图案化的光致抗蚀剂层完全依次形成在基板上。通过使用图案化的光致抗蚀剂层作为掩模并且部分地去除保护层来形成图案化的保护层，其中图案化的保护层具有位于其侧壁处的底切。形成像素电极材料层以覆盖衬底，TFT和图案化光致抗蚀剂层，其中电极材料层在底切处断开并暴露底切。电连接到TFT的像素电极通过剥离图案化的光致抗蚀剂层和覆盖图案化的光致抗蚀剂层的电极材料层的部分同时通过剥离器形成，其中剥离剂从底切渗透到图案化的光致抗蚀剂层和图案化保护层。

7. 发明申请

US20090053844A1 METHOD FOR FABRICATING PIXEL STRUCTURE 审中-公开
标题翻译：制造像素结构的方法
公开(公告)号：US20090053844A1
公开(公告)日：2009-02-26
申请号：US12050928
申请日：2008-03-18
申请人： Ming-Yuan Huang , Chih-Chun Yang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Chin-Yueh Liao , Chia-Chi Tsai
发明人： Ming-Yuan Huang , Chih-Chun Yang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Chin-Yueh Liao , Chia-Chi Tsai
IPC分类号： H01L33/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1255
摘要： A method for fabricating a pixel structure is provided. A substrate having a gate thereon is provided. Next, a gate dielectric layer is formed to cover the gate. A channel layer is formed on the gate dielectric layer above the gate. A source and a drain are formed on the channel layer at two sides of the gate, wherein the gate, the channel layer, the source and the drain constitute a thin film transistor (TFT). A passivation layer is formed on the gate dielectric layer and the TFT. A first shadow mask exposing parts of the passivation layer is provided thereabove. The drain is exposed by a laser applied via the first shadow mask to partially remove the passivation layer. A conductive layer is formed to cover the passivation layer and the drain. The conductive layer is then automatically patterned by the patterned passivation layer to form a pixel electrode.
摘要翻译：提供了一种用于制造像素结构的方法。提供了具有栅极的基板。接下来，形成栅极电介质层以覆盖栅极。沟道层形成在栅极上方的栅极电介质层上。源极和漏极形成在栅极两侧的沟道层上，其中栅极，沟道层，源极和漏极构成薄膜晶体管（TFT）。在栅极电介质层和TFT上形成钝化层。暴露部分钝化层的第一荫罩在其上方设置。漏极通过经由第一荫罩施加的激光曝光以部分地去除钝化层。形成导电层以覆盖钝化层和漏极。导电层然后通过图案化的钝化层自动图案化以形成像素电极。

8. 发明授权

US08420463B2 Method for manufacturing pixel structure 有权
标题翻译：像素结构制造方法
公开(公告)号：US08420463B2
公开(公告)日：2013-04-16
申请号：US13163774
申请日：2011-06-20
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Chin-Yueh Liao
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Chin-Yueh Liao
IPC分类号： H01L21/00 , H01L21/84 , H01L27/118 , H01L23/52
CPC分类号： H01L29/458 , H01L27/124 , H01L27/1288
摘要： A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.
摘要翻译：像素结构包括扫描线，数据线，有源元件，第一钝化层，第二钝化层和像素电极。数据线包括第一数据金属段和第二数据金属层。有源元件包括栅电极，绝缘层，沟道层，源极和漏极。沟道层位于栅电极上方的绝缘层上。源极和漏极位于沟道层上。源耦合到数据线。第一钝化层和第二钝化层覆盖有源元件并形成第一接触孔以暴露漏极的一部分。第二钝化层覆盖漏极的一部分边缘。像素电极跨越第二钝化层设置并且经由第一接触孔耦合到漏极。

9. 发明申请

US20110244615A1 METHOD FOR MANUFACTURING PIXEL STRUCTURE 有权
标题翻译：制造像素结构的方法
公开(公告)号：US20110244615A1
公开(公告)日：2011-10-06
申请号：US13163774
申请日：2011-06-20
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Chin-Yueh Liao
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Chin-Yueh Liao
IPC分类号： H01L21/70
CPC分类号： H01L29/458 , H01L27/124 , H01L27/1288
摘要： A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.
摘要翻译：像素结构包括扫描线，数据线，有源元件，第一钝化层，第二钝化层和像素电极。数据线包括第一数据金属段和第二数据金属层。有源元件包括栅电极，绝缘层，沟道层，源极和漏极。沟道层位于栅电极上方的绝缘层上。源极和漏极位于沟道层上。源耦合到数据线。第一钝化层和第二钝化层覆盖有源元件并形成第一接触孔以暴露漏极的一部分。第二钝化层覆盖漏极的一部分边缘。像素电极跨越第二钝化层设置并且经由第一接触孔耦合到漏极。

10. 发明申请

US20090191652A1 Pixel structure and method for manufacturing the same 审中-公开
标题翻译：像素结构及其制造方法
公开(公告)号：US20090191652A1
公开(公告)日：2009-07-30
申请号：US12081515
申请日：2008-04-17
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Chin-Yueh Liao
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Chin-Yueh Liao
IPC分类号： H01L27/02 , H01L21/70
CPC分类号： H01L29/458 , H01L27/124 , H01L27/1288
摘要： A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.
摘要翻译：像素结构包括扫描线，数据线，有源元件，第一钝化层，第二钝化层和像素电极。数据线包括第一数据金属段和第二数据金属层。有源元件包括栅电极，绝缘层，沟道层，源极和漏极。沟道层位于栅电极上方的绝缘层上。源极和漏极位于沟道层上。源耦合到数据线。第一钝化层和第二钝化层覆盖有源元件并形成第一接触孔以暴露漏极的一部分。第二钝化层覆盖漏极的一部分边缘。像素电极跨越第二钝化层设置并且经由第一接触孔耦合到漏极。

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