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1. 发明授权

US6048762A Method of fabricating embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器的制作方法
公开(公告)号：US6048762A
公开(公告)日：2000-04-11
申请号：US55577
申请日：1998-04-06
申请人： Liang-Choo Hsia , H. J. Wu
发明人： Liang-Choo Hsia , H. J. Wu
IPC分类号： H01L21/285 , H01L21/8242 , H01L27/108 , H01L21/8244
CPC分类号： H01L27/10852 , H01L21/28512 , H01L27/10808
摘要： A method of fabricating an embedded dynamic random access memory. Using the method of dual damascence, by forming patterning only one dielectric layer, the contact windows with different depth are formed. In addition, the metal layer formed within the metal connecting regions are used as interconnects without further process.
摘要翻译：一种制造嵌入式动态随机存取存储器的方法。使用双重阻力的方法，通过仅形成图案化的一个电介质层，形成具有不同深度的接触窗口。此外，形成在金属连接区域内的金属层用作互连而不进一步处理。

2. 发明申请

US20110316166A1 INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：集成电路系统及其制造方法
公开(公告)号：US20110316166A1
公开(公告)日：2011-12-29
申请号：US12825266
申请日：2010-06-28
申请人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
发明人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/7684
摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.
摘要翻译：集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

3. 发明授权

US07445874B2 Method to resolve line end distortion for alternating phase shift mask 有权
标题翻译：解决交变相移掩模线路失真的方法
公开(公告)号：US07445874B2
公开(公告)日：2008-11-04
申请号：US10985263
申请日：2004-11-10
申请人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
发明人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/30
摘要： A embodiment method for forming a layout for a phase shift mask. A embodiment comprises providing a layout comprising a first feature, a first shifter region and a second shifter region. The first feature preferably has a L-shape portion with an elbow region. The first shifter region is on the outside of the L-shaped portion and the second shifter region is on the inside of the L-shaped portion. The elbow region has an outside corner away from the second shifter region. We identify a phase conflict region caused by the L-shaped portion of the first feature, the first shifter region and the second shifter region. We resolve the phase conflict by modifying the elbow region by moving the outside corner of the elbow region away from the first shifter region and the phase conflict region. The modification of the elbow region further comprises forming a jog region in the line end section of the first feature.
摘要翻译：一种用于形成相移掩模布局的实施例方法。实施例包括提供包括第一特征，第一移位区和第二移位区的布局。第一特征优选具有肘部区域的L形部分。第一移位区域位于L形部分的外侧，第二移位区域位于L形部分的内侧。肘部区域具有远离第二移位区域的外角。我们识别由第一特征的L形部分，第一移位区域和第二移位区域引起的相位冲突区域。我们通过移动肘部区域的外角远离第一移位区域和相位冲突区域来修改肘部区域来解决相位冲突。肘部区域的修改还包括在第一特征的线端部中形成点动区域。

4. 发明授权

US5851898A Method of forming stacked capacitor having corrugated side-wall structure 失效
标题翻译：形成具有波纹状侧壁结构的叠层电容器的方法
公开(公告)号：US5851898A
公开(公告)日：1998-12-22
申请号：US697442
申请日：1996-08-23
申请人： Liang-Choo Hsia , Thomas Chang
发明人： Liang-Choo Hsia , Thomas Chang
IPC分类号： H01L21/02 , H01L21/311 , H01L21/316 , H01L21/768 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31111 , H01L21/31612 , H01L28/87 , H01L21/76895 , H01L28/88
摘要： A method of forming a capacitor that has improved charge storage capability and a capacitor produced by such method are provided. The method utilizes an additional layer of oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with a substantially increased surface area leading to an improved charge storage capability.
摘要翻译：提供一种形成具有改善的电荷存储能力的电容器的方法和通过这种方法制造的电容器。该方法利用由通过热CVD和等离子体CVD的两种交替方法沉积的多个氧化物层组成的附加的氧化物间隔层。在通过等离子体蚀刻技术首先蚀刻接触孔之后，通过诸如氟化氢的蚀刻剂再次蚀刻该孔，其对通过等离子体CVD法形成的氧化物层具有高选择性，并且对由热 CVD法。结果，形成接触孔的波纹状侧壁，其使电容器单元具有显着增加的表面积，从而提高电荷存储能力。

5. 发明授权

US5789267A Method of making corrugated cell contact 失效
标题翻译：波纹细胞接触的方法
公开(公告)号：US5789267A
公开(公告)日：1998-08-04
申请号：US702747
申请日：1996-08-23
申请人： Liang-Choo Hsia , Thomas Chang
发明人： Liang-Choo Hsia , Thomas Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87
摘要： A method of forming a cell contact that has improved structural strength and break-down resistance and a cell contact produced by such method are provided. The method utilizes an oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a straight contact opening is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a contact opening having a corrugated side-wall is formed and into which a polysilicon is deposited to substantially fill the hole. A cell contact having a corrugated side-wall configuration is thus formed which presents improved structural rigidity and break-down resistance. A layer of rugged polysilicon layer may optionally be deposited before the deposition of the polysilicon into the contact opening to further increase the surface area of the cell contact.
摘要翻译：提供了一种形成具有改进的结构强度和耐断裂性的电池接触的方法以及通过这种方法制造的电池接触。该方法利用由通过热CVD和等离子体CVD的两种交替方法沉积的多个氧化物层组成的氧化物间隔物。在通过等离子体蚀刻技术首先蚀刻直接接触开口之后，再次通过诸如氟化氢的蚀刻剂蚀刻该孔，其对通过等离子体CVD法形成的氧化物层具有高选择性，并且对由热CVD法。结果，形成具有波形侧壁的接触开口，并且沉积多晶硅以基本上填充该孔。由此形成具有波纹状的侧壁结构的电池触点，其具有改善的结构刚性和耐断裂性。在将多晶硅沉积到接触开口中之前，可以任选地沉积一层坚固的多晶硅层，以进一步增加电池接触的表面积。

6. 发明授权

US5633522A CMOS transistor with two-layer inverse-T tungsten gate 失效
标题翻译： CMOS晶体管具有双层反T钨栅极
公开(公告)号：US5633522A
公开(公告)日：1997-05-27
申请号：US648457
申请日：1996-05-15
申请人： Fernand Dorleans , Liang-Choo Hsia , Louis L. C. Hsu , Gerald R. Larsen , Geraldine C. Schwartz
发明人： Fernand Dorleans , Liang-Choo Hsia , Louis L. C. Hsu , Gerald R. Larsen , Geraldine C. Schwartz
IPC分类号： H01L29/43 , H01L21/225 , H01L21/28 , H01L21/3213 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L21/2256 , H01L21/28079 , H01L21/28114 , H01L21/32134 , H01L21/32136 , H01L29/6656
摘要： The present invention is directed to a unique silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.
摘要翻译：本发明涉及一种具有逆T难熔金属栅极结构的独特的硅基MOS晶体管。根据本发明制造的门包括主CVD钨部分和从CVD部分的底部向外延伸的下溅射钨部分，使得栅极的横截面呈现为倒置的“T”。使用Cl2 / O2等离子体蚀刻来蚀刻CVD钨层，并且使用化学蚀刻来蚀刻溅射的钨层以形成栅电极。已经发现，溅射钨比CVD钨更耐Cl2 / O2反应离子蚀刻。溅射的钨层用作屏蔽，以在整个制造过程中保护底层的栅极氧化物层免受离子损伤。

7. 发明授权

US5135595A Process for fabricating a low dielectric composite substrate 失效
标题翻译：制造低介电复合基板的工艺
公开(公告)号：US5135595A
公开(公告)日：1992-08-04
申请号：US503495
申请日：1990-03-30
申请人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
发明人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
IPC分类号： H05K1/03 , C04B41/48 , C04B41/49 , H01L21/48 , H01L23/08 , H01L23/538 , H05K3/40
CPC分类号： H01L21/4857 , C04B41/488 , C04B41/4961 , H01L23/5383 , H05K3/4061 , C04B2111/00672 , C04B2111/00844 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H05K1/0306 , H05K2201/09581 , H05K2203/1147 , H05K2203/308
摘要： The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addresssed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

8. 发明授权

US08536705B2 Integrated circuit system with through silicon via and method of manufacture thereof 有权
标题翻译：具有硅通孔的集成电路系统及其制造方法
公开(公告)号：US08536705B2
公开(公告)日：2013-09-17
申请号：US13455152
申请日：2012-04-25
申请人： Pradeep Ramachandramurthy Yelehanka , Denise Tan , Chung Meng Lek , Thomas Thiam , Jeffrey C. Lam , Liang-Choo Hsia
发明人： Pradeep Ramachandramurthy Yelehanka , Denise Tan , Chung Meng Lek , Thomas Thiam , Jeffrey C. Lam , Liang-Choo Hsia
IPC分类号： H01L23/48
CPC分类号： H01L21/823878 , H01L21/76898 , H01L21/823871 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
摘要翻译：一种集成电路系统的制造方法，包括：提供包括有源器件的衬底; 在所述衬底中形成穿硅通孔; 在穿通硅通孔上形成绝缘层，以保护穿硅通孔; 在形成绝缘层之后形成与有源器件的接触; 并去除绝缘层。

9. 发明申请

US20100297844A1 INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：通过硅的集成电路系统及其制造方法
公开(公告)号：US20100297844A1
公开(公告)日：2010-11-25
申请号：US12470028
申请日：2009-05-21
申请人： Pradeep Ramachandramurthy Yelehanka , Denise Tan , Chung Meng Lek , Thomas Thiam , Jeffrey C. Lam , Liang-Choo Hsia
发明人： Pradeep Ramachandramurthy Yelehanka , Denise Tan , Chung Meng Lek , Thomas Thiam , Jeffrey C. Lam , Liang-Choo Hsia
IPC分类号： H01L21/768
CPC分类号： H01L21/823878 , H01L21/76898 , H01L21/823871 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
摘要翻译：一种集成电路系统的制造方法，包括：提供包括有源器件的衬底; 在所述衬底中形成穿硅通孔; 在穿通硅通孔上形成绝缘层，以保护穿硅通孔; 在形成绝缘层之后形成与有源器件的接触; 并去除绝缘层。

10. 发明申请

US20080145795A1 SEMICONDUCTOR PROCESSING SYSTEM WITH ULTRA LOW-K DIELECTRIC 有权
标题翻译：具有超低K电介质的半导体处理系统
公开(公告)号：US20080145795A1
公开(公告)日：2008-06-19
申请号：US11613155
申请日：2006-12-19
申请人： Yasri Yudhistira , Johnny Widodo , Bei Chao Zhang , Liang-Choo Hsia
发明人： Yasri Yudhistira , Johnny Widodo , Bei Chao Zhang , Liang-Choo Hsia
IPC分类号： G03F7/00
CPC分类号： G03F7/0035 , H01L21/3105 , H01L21/31111 , H01L21/31133 , H01L21/76802 , H01L21/7682 , H01L21/76825 , H01L2221/1047
摘要： A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.
摘要翻译：提供了一种具有超低K电介质的半导体处理系统，包括提供具有电子电路的衬底，在衬底上形成具有致孔剂的超低K电介质层，阻挡来自超低K电介质的第一区域的入射辐射， K电介质层，通过将入射辐射投射在第二区域上，从超低K电介质层的第二区域蒸发致孔剂，并用显影剂除去第一区域中的超低K电介质层。

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