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1. 发明授权

US08242608B2 Universal bump array structure 有权
标题翻译：通用凸块阵列结构
公开(公告)号：US08242608B2
公开(公告)日：2012-08-14
申请号：US12242674
申请日：2008-09-30
申请人： Li-Tien Chang , Yuanlin Xie
发明人： Li-Tien Chang , Yuanlin Xie
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/3128 , H01L24/17 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/1411 , H01L2224/14131 , H01L2224/16225 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A bump array structure for an integrated circuit is presented. An array of metal alloy bumps is disposed on a surface of the integrated circuit. The array of metal alloy bumps is configured to receive input from a multi-layer substrate package and transmit output to the multi-layer substrate package. The array defines a first portion of metal alloy bumps around the periphery of the surface of the integrated circuit configured to provide power and ground signals for the integrated circuit. The array further defines a second portion of metal alloy bumps providing power and ground for the integrated circuit, located between opposing sides of the periphery of the integrated circuit. Metal alloy bumps not contained in either the first or the second portion of the array are configured for input and output signals between the integrated circuit and the multi-level substrate package.
摘要翻译：提出了一种用于集成电路的凸块阵列结构。金属合金凸块阵列设置在集成电路的表面上。金属合金凸块的阵列被配置为从多层衬底封装接收输入并将输出传输到多层衬底封装。阵列限定围绕集成电路的表面的周边的金属合金凸块的第一部分，其被配置为为集成电路提供电力和接地信号。阵列进一步限定金属合金凸块的第二部分，为集成电路提供功率和接地，位于集成电路外围的相对侧之间。不包含在阵列的第一或第二部分中的金属合金凸块被配置用于集成电路和多电平衬底封装之间的输入和输出信号。

2. 发明申请

US20100078207A1 UNIVERSAL BUMP ARRAY STRUCTURE 有权
标题翻译：通用阵列阵列结构
公开(公告)号：US20100078207A1
公开(公告)日：2010-04-01
申请号：US12242674
申请日：2008-09-30
申请人： Li-Tien Chang , Yuanlin Xie
发明人： Li-Tien Chang , Yuanlin Xie
IPC分类号： H01R12/30
CPC分类号： H01L23/50 , H01L23/3128 , H01L24/17 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/1411 , H01L2224/14131 , H01L2224/16225 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A bump array structure for an integrated circuit is presented. An array of metal alloy bumps is disposed on a surface of the integrated circuit. The array of metal alloy bumps is configured to receive input from a multi-layer substrate package and transmit output to the multi-layer substrate package. The array defines a first portion of metal alloy bumps around the periphery of the surface of the integrated circuit configured to provide power and ground signals for the integrated circuit. The array further defines a second portion of metal alloy bumps providing power and ground for the integrated circuit, located between opposing sides of the periphery of the integrated circuit. Metal alloy bumps not contained in either the first or the second portion of the array are configured for input and output signals between the integrated circuit and the multi-level substrate package
摘要翻译：提出了一种用于集成电路的凸块阵列结构。金属合金凸块阵列设置在集成电路的表面上。金属合金凸块的阵列被配置为从多层衬底封装接收输入并将输出传输到多层衬底封装。阵列限定围绕集成电路的表面的周边的金属合金凸块的第一部分，其被配置为为集成电路提供电力和接地信号。阵列进一步限定金属合金凸块的第二部分，为集成电路提供功率和接地，位于集成电路外围的相对侧之间。不包含在阵列的第一或第二部分中的金属合金凸块被配置用于集成电路和多级衬底封装之间的输入和输出信号

3. 发明授权

US09401330B1 IC package with non-uniform dielectric layer thickness 有权
标题翻译： IC封装具有不均匀的介电层厚度
公开(公告)号：US09401330B1
公开(公告)日：2016-07-26
申请号：US12578426
申请日：2009-10-13
申请人： Xiaohong Jiang , Hong Shi , Hui Liu , Yuanlin Xie
发明人： Xiaohong Jiang , Hong Shi , Hui Liu , Yuanlin Xie
IPC分类号： H01L23/538 , H01L23/12
CPC分类号： H01L23/5383 , H01L23/12 , H01L23/49822 , H01L23/50 , H01L23/64 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00 , H01L2924/014
摘要： An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.
摘要翻译：公开了具有不均匀电介质层的集成电路（IC）封装基板。 IC封装基板是具有交替堆叠的电介质层和金属层的多层封装基板。封装衬底中的电介质层具有不同的厚度。金属层可以是接地，信号或功率层。在封装衬底中的信号层和功率层之间放置较厚的介电层。较厚的电介质层可以是封装衬底中其它电介质层的至少两倍。较厚的介电层可以在封装衬底中提供更好的阻抗控制。

4. 发明授权

US08198699B1 Integrated circuit package with non-solder mask defined like pads 有权
标题翻译：集成电路封装，非焊锡掩模定义为焊盘
公开(公告)号：US08198699B1
公开(公告)日：2012-06-12
申请号：US12762958
申请日：2010-04-19
申请人： Yuanlin Xie , Yuan Li
发明人： Yuanlin Xie , Yuan Li
IPC分类号： H01L21/70
CPC分类号： H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227
摘要： Provided is an IC package. In one implementation, the IC package includes a metal pad having a first metal pad surface and a second metal pad surface substantially parallel to the first metal pad surface; a first dielectric layer having a first surface, a second surface, and a third surface, where the first dielectric layer covers a first end portion of the second metal pad surface, and the third surface of the first dielectric layer is substantially parallel to the first and second surfaces of the first dielectric layer; a second dielectric layer having a first surface, a second surface, and a third surface, where the second dielectric layer covers a second end portion of the second metal pad surface, and the third surface of the second dielectric layer is substantially parallel to the first and second surfaces of the second dielectric layer; and a metal structure covering a middle portion of the second metal pad surface, a first end portion of the third surface of the first dielectric layer, and a first end portion of the third surface of the second dielectric layer.
摘要翻译：提供了一个IC封装。在一个实施方案中，IC封装包括具有第一金属焊盘表面和基本上平行于第一金属焊盘表面的第二金属焊盘表面的金属焊盘; 具有第一表面，第二表面和第三表面的第一电介质层，其中所述第一电介质层覆盖所述第二金属焊盘表面的第一端部，并且所述第一电介质层的所述第三表面基本上平行于所述第一电介质层和第一介电层的第二表面; 具有第一表面，第二表面和第三表面的第二介电层，其中所述第二介电层覆盖所述第二金属焊盘表面的第二端部，并且所述第二介电层的所述第三表面基本上平行于所述第一表面和第二介电层的第二表面; 以及覆盖第二金属焊盘表面的中间部分，第一电介质层的第三表面的第一端部分和第二电介质层的第三表面的第一端部的金属结构。

5. 发明申请

US20110204476A1 Electronic Package with Fluid Flow Barriers 失效
标题翻译：具有流体流动障碍的电子封装
公开(公告)号：US20110204476A1
公开(公告)日：2011-08-25
申请号：US13019815
申请日：2011-02-02
申请人： Teck-Gyu Kang , Yuan Li , Yuanlin Xie
发明人： Teck-Gyu Kang , Yuan Li , Yuanlin Xie
IPC分类号： H01L29/02
CPC分类号： H01L21/563 , H01L23/16 , H01L2224/16225 , H01L2224/26175 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/15311 , H01L2924/19105 , H01L2924/00 , H01L2924/00012
摘要： The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.
摘要翻译：本发明涉及一种方法和电子计算机包装，该方法和电子计算机包装通过放置集成电路而形成，该集成电路具有多个焊盘，其上沉积有焊料凸块，与衬底接触，使得多个焊料凸块中的一个叠加相对于触点之一和多个接合焊盘中的一个，其中在与集成电路叠加的基板的区域之间限定了体积。体积的一部分充满了一定量的底部填充物。在衬底上形成流体流动泳池并且限定容积的周长，限定流动限制区域。流体流动阻挡层具有足以控制从流动限制区域排出的底部填充物的量的尺寸。

6. 发明授权

US07936059B1 Lead frame packaging technique with reduced noise and cross-talk 有权
标题翻译：引线框架封装技术，减少噪音和串扰
公开(公告)号：US07936059B1
公开(公告)日：2011-05-03
申请号：US11676864
申请日：2007-02-20
申请人： Yuanlin Xie
发明人： Yuanlin Xie
IPC分类号： H01L23/495 , H01L23/498 , H01L23/28 , H01L23/48 , H01L23/31
CPC分类号： H01L23/3107 , H01L23/49861 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/484 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： Broadly speaking, the present invention fills these needs by providing a lead frame package including a substrate stack having opposed sides, one of which includes a plurality of signal traces, with the remaining side including a ground plane. An integrated circuit is mounted to the substrate stack. The integrated circuit includes a plurality of bond pads. A plurality of leads is in electrical communication with a subset of the plurality of signal traces. A plurality of electrically conductive elements placing a sub-group of the plurality of bond pads in electrical communication with a sub-part of the plurality of electrically leads by being bonded signal traces of the subset, spaced-apart from the plurality of leads.
摘要翻译：广义而言，本发明通过提供一种引线框架封装来满足这些需要，引线框架封装包括具有相对侧面的衬底叠层，其中一个包括多个信号迹线，其余侧面包括接地层。集成电路安装到衬底叠层。集成电路包括多个接合焊盘。多个引线与多个信号迹线的子集电连通。多个导电元件将多个接合焊盘的子组与多个电引线的子部分电连通，通过与多个引线间隔开的子集的结合信号迹线。

7. 发明授权

US07309912B1 On-package edge-mount power decoupling and implementation with novel substrate design for FPGA and ASIC devices 有权
标题翻译：封装边缘安装电源去耦和实现，为FPGA和ASIC器件提供新颖的基板设计
公开(公告)号：US07309912B1
公开(公告)日：2007-12-18
申请号：US11478017
申请日：2006-06-28
申请人： Hong Shi , Yuanlin Xie , Tarun Verma
发明人： Hong Shi , Yuanlin Xie , Tarun Verma
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/3675 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01322 , H01L2924/10253 , H01L2924/3011 , H01L2924/00
摘要： A package substrate is provided with a side/edge-mounted decoupling capacitor that can provide substantially instant power or control simultaneous switching noise (SSN) associated with a semiconductor device package. A fabrication method for such a package substrate is also provided. Further, a semiconductor device package that includes such a package substrate is provided. According to various embodiments, the decoupling capacitor is connected to edges or sides of a power plane and a ground plane in the package substrate for connection via the semiconductor device package's power delivery system to a power source or component.
摘要翻译：封装基板设置有侧/边缘安装的去耦电容器，其可以提供与半导体器件封装相关联的基本即时功率或控制同时开关噪声（SSN）。还提供了一种用于这种封装衬底的制造方法。此外，提供了包括这种封装基板的半导体器件封装。根据各种实施例，去耦电容器连接到封装衬底中的功率平面和接地平面的边缘或侧面，用于经由半导体器件封装的功率输送系统连接到电源或组件。

8. 发明申请

US20060175710A1 Consolidated flip chip BGA assembly process and apparatus 有权
标题翻译：合并倒装芯片BGA装配工艺及装置
公开(公告)号：US20060175710A1
公开(公告)日：2006-08-10
申请号：US11056821
申请日：2005-02-10
申请人： Yuanlin Xie
发明人： Yuanlin Xie
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L21/50 , H01L21/563 , H01L21/565 , H01L23/055 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2224/83102 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/16195 , H01L2224/0401
摘要： A flip chip packaging technique and associated apparatus that consolidates many or all of the steps in a conventional flip chip packaging process results in substantially decreased packaging time, e.g., only one to two hours, complexity, e.g., requiring fewer pieces and much simpler equipment, and cost, arising from reduced equipment operation and maintenance time and decreased labor. An assembly fixture useful for implementing the consolidated assembly technique engages and holds in place a semiconductor flip chip die with a plurality semiconductor package components in a desired package configuration so that they can be assembled into a semiconductor package with a single application of heat and pressure.
摘要翻译：一种倒装芯片封装技术和相关设备，其在常规的倒装芯片封装工艺中整合许多或所有步骤，从而实现了大大减少的封装时间，例如只有一到两个小时的复杂性，例如需要更少的件和更简单的设备，和成本，由于设备运行和维护时间缩短，劳动力减少。用于实现固结的组装技术的装配夹具将具有多个半导体封装部件的半导体倒装芯片裸片并且保持在期望的封装结构中，使得它们可以通过单次施加热和压力而组装成半导体封装。

9. 发明申请

US20130069247A1 APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS 有权
标题翻译：堆叠式电子电路及相关方法的设备
公开(公告)号：US20130069247A1
公开(公告)日：2013-03-21
申请号：US13235166
申请日：2011-09-16
申请人： Arifur Rahman , Jon M. Long , Yuanlin Xie
发明人： Arifur Rahman , Jon M. Long , Yuanlin Xie
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/0652 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2924/12042 , H01L2924/15153 , H01L2924/15311 , H01L2924/15321 , H05K1/141 , H05K3/4697 , H05K2201/1053 , H01L2924/014 , H01L2924/00
摘要： An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.
摘要翻译：一种装置包括基板和包括电子电路的一对管芯。基板包括空腔。模具中的一个设置在形成在基板中的空腔中。另一个管芯设置在第一管芯上方并且电耦合到第一管芯。

10. 发明授权

US07472367B1 Method of optimizing interconnect distribution to improve signal integrity 失效
标题翻译：优化互连分布以提高信号完整性的方法
公开(公告)号：US07472367B1
公开(公告)日：2008-12-30
申请号：US11262347
申请日：2005-10-27
申请人： Yuanlin Xie , Hong Shi
发明人： Yuanlin Xie , Hong Shi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of distributing an array of interconnects on an electronic device divides the array into multiple regions, each region having certain performance requirements. For each region, predefined performance curves are used to choose from a plurality of interconnect distribution pattern modules one or more interconnect distribution pattern modules that satisfy the corresponding performance requirements. The chosen interconnect distribution pattern modules are used to generate a performance indication map highlighting those vulnerable interconnect(s) that may suffer severe crosstalk interference. Each vulnerable interconnect is then relocated to a different location until the performance requirements are met.
摘要翻译：在电子设备上分配互连阵列的方法将阵列划分成多个区域，每个区域具有一定的性能要求。对于每个区域，使用预定义的性能曲线来从多个互连分布模式模块中选择满足相应性能要求的一个或多个互连分布模式模块。选择的互连分布模式模块用于生成突出显示可能遭受严重串扰干扰的那些易受攻击的互连的性能指示图。然后将每个易受攻击的互连重新定位到不同的位置，直到满足性能要求。

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