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1. 发明授权

US5729181A High thermal gain oven with reduced probability of temperature gradient formation for the operation of a thermally stable oscillator 失效
标题翻译：高热增益炉，降低了热稳定振荡器运行温度梯度形成的可能性
公开(公告)号：US5729181A
公开(公告)日：1998-03-17
申请号：US702075
申请日：1996-08-23
申请人： Leonard S. Cutler , Richard K. Karlquist , James R. Collin , James L. Johnson , Theodore Parisek , Robin P. Giffard
发明人： Leonard S. Cutler , Richard K. Karlquist , James R. Collin , James L. Johnson , Theodore Parisek , Robin P. Giffard
IPC分类号： H03B5/32 , G05D23/24 , H03L1/04
CPC分类号： H03L1/04 , G05D23/1931 , G05D23/24
摘要： An oven assembly for a crystal resonator and oscillator utilizes a thermally symmetrical design to provide a high thermal gain. The oven assembly includes an encasement that forms a hermetically sealed oven chamber that is substantially cylindrical. Concentric with the oven chamber is an annular oven mass that functions as a heat reservoir for the crystal resonator that is contained within the oven mass. The cylindrical oven chamber and the concentric annular oven mass provide two levels of circular symmetry that help achieve a thermally isotropic oscillator environment. Wide-area uniform heat transfer promotes high thermal gain and minimizes thermal gradients. Another factor is the geometry and circuitry for temperature monitoring. Temperature sensors are equidistantly spaced from each other and are equidistant from the center of the oven chamber. Signals from the various thermistors are averaged to provide a more accurate temperature determination for regulating the heaters.
摘要翻译：用于晶体谐振器和振荡器的烤箱组件利用热对称设计来提供高热增益。烤箱组件包括形成基本上圆柱形的气密密封的烤箱室的外壳。与烤箱室同心的是一种环形烤箱，用作包含在烤箱中的晶体谐振器的储热器。圆柱形烤箱室和同心环形烤箱质量提供了两个等级的圆形对称，有助于实现热各向同性的振荡器环境。广泛的均匀传热促进了高的热增益并使热梯度最小化。另一个因素是温度监测的几何和电路。温度传感器彼此距离相等并且距离烘箱的中心等距。将各种热敏电阻的信号平均，以提供更准确的温度测定来调节加热器。

2. 发明授权

US06651488B2 Systems and methods of monitoring thin film deposition 有权
公开(公告)号：US06651488B2
公开(公告)日：2003-11-25
申请号：US10266857
申请日：2002-10-07
申请人： John D. Larson, III , Herbert L. Ko , Richard K. Karlquist , Mark A. Hueschen , Kent W. Carey
发明人： John D. Larson, III , Herbert L. Ko , Richard K. Karlquist , Mark A. Hueschen , Kent W. Carey
IPC分类号： G01N3300
CPC分类号： G01N29/4436 , C23C14/546 , G01N29/036 , G01N29/30
摘要： Systems and methods of monitoring thin film deposition are described. In one aspect, a thin film deposition sensor includes an acoustical resonator (e.g., a thin film bulk acoustical resonator) that has an exposed surface and is responsive to thin film material deposits on the exposed surface. A substrate clip may be configured to attach the thin film deposition sensor to a substrate. A transceiver circuit may be configured to enable the thin film deposition sensor to be interrogated wirelessly. A method of monitoring a thin film deposition on a substrate also is described.

3. 发明授权

US07245683B2 System and methods of recovering a clock from NRZ data 失效
标题翻译：从NRZ数据恢复时钟的系统和方法
公开(公告)号：US07245683B2
公开(公告)日：2007-07-17
申请号：US10411996
申请日：2003-04-11
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H04L7/02
CPC分类号： H04L7/027 , H04L7/033
摘要： A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an inverted NRZ signal are received). The inverted NRZ data may be delayed by one-half of a unit interval with respect to the NRZ data by a delay element. The NRZ data and the delayed NRZ data may be combined by a broadband combiner (e.g., a resistive adder). The combined signal may be split into two signals. The two split signals may be rectified by suitable components. One of the limited split signals may be subtracted from the other limited split signal to generate an output signal. The generated output signal then possesses a spectral component at a clock frequency of the NRZ data.
摘要翻译：可以采用时钟恢复电路的基本被动的实现来减少或消除由恢复电路添加到恢复时钟的抖动量。可以以差分形式接收NRZ数据（即，接收到单独的NRZ信号和反相NRZ信号）。反向NRZ数据可以通过延迟元件相对于NRZ数据被延迟单位间隔的二分之一。 NRZ数据和延迟的NRZ数据可以由宽带组合器（例如，电阻加法器）组合。组合信号可以被分成两个信号。两个分离信号可以由适当的部件整流。有限分割信号中的一个可以从另一个有限分割信号中减去以产生输出信号。所产生的输出信号随后在NRZ数据的时钟频率处具有频谱分量。

4. 发明授权

US06765435B2 Phase locked loop demodulator and demodulation method using feed-forward tracking error compensation 失效
标题翻译：使用前馈跟踪误差补偿的锁相环解调器和解调方法
公开(公告)号：US06765435B2
公开(公告)日：2004-07-20
申请号：US10328363
申请日：2002-12-23
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H03D324
CPC分类号： H03D3/248
摘要： In embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalized is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. A similar arrangement including a suitably calibrated equalizer may be utilized to address phase tracking error in a PLL frequency demodulator.
摘要翻译：在实施例中，本发明涉及利用前馈误差校正的PLL相位解调器。通过校准均衡器以具有模拟PLL相位解调器的VCO的调制响应曲线的传递函数，可以进行前馈纠错。在操作中，均衡器可以接收由PLL的相位检测器产生的误差信号的滤波和积分版本。均衡器根据校准传递函数对接收到的信号进行滤波。均衡的输出被提供给加法器，以将均衡的信号与由相位检测器产生的误差信号组合。可以使用包括适当校准的均衡器的类似布置来解决PLL频率解调器中的相位跟踪误差。

5. 发明授权

US5708394A Bridge-stabilized oscillator circuit and method 失效
标题翻译：桥式稳压振荡电路及方法
公开(公告)号：US5708394A
公开(公告)日：1998-01-13
申请号：US671300
申请日：1996-07-01
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H03L7/00 , H03B1/00 , H03B5/38 , H03L5/00 , H03L7/02 , H03B5/32
CPC分类号： H03L5/00 , H03B5/38 , H03L7/02 , H03B2201/0208 , H03B2201/031
摘要： An apparatus and method are disclosed for improving the stability of the frequency of vibration of an oscillator signal produced by an oscillator circuit. In a preferred embodiment of the present invention, a quartz crystal resonator is one arm of a bridge which generates a bridge signal which varies in accordance with the vibrating frequency of the resonator. A synchronous demodulator responds to the bridge signal for producing an error signal which is converted into a control signal. A control circuit receives the control signal and changes its reactance when the resonator is no longer vibrating at its unperturbed resonance frequency so that the vibration frequency of the resonator connected to the control circuit is returned to its resonant frequency. An automatic level control circuit is also included for controlling the drive level of the signal exciting the resonator.
摘要翻译：公开了一种用于改善由振荡器电路产生的振荡器信号的振动频率的稳定性的装置和方法。在本发明的优选实施例中，石英晶体谐振器是桥的一个臂，其产生根据谐振器的振动频率而变化的桥接信号。同步解调器响应于桥信号以产生被转换成控制信号的误差信号。当谐振器在其未扰动的谐振频率下不再振动时，控制电路接收控制信号并改变其电抗，使得连接到控制电路的谐振器的振动频率返回到其谐振频率。还包括用于控制激励谐振器的信号的驱动电平的自动电平控制电路。

6. 发明授权

US07177380B2 System and methods of recovering a clock from NRZ data 有权
公开(公告)号：US07177380B2
公开(公告)日：2007-02-13
申请号：US10411996
申请日：2003-04-11
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H04L7/02
摘要： A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an inverted NRZ signal are received). The inverted NRZ data may be delayed by one-half of a unit interval with respect to the NRZ data by a delay element. The NRZ data and the delayed NRZ data may be combined by a broadband combiner (e.g., a resistive adder). The combined signal may be split into two signals. The two split signals may be rectified by suitable components. One of the limited split signals may be subtracted from the other limited split signal to generate an output signal. The generated output signal then possesses a spectral component at a clock frequency of the NRZ data.

7. 发明授权

US07173995B2 Systems and methods for correcting gain error due to transition density variation in clock recovery systems 失效
标题翻译：用于校正由于时钟恢复系统中的转换密度变化引起的增益误差的系统和方法
公开(公告)号：US07173995B2
公开(公告)日：2007-02-06
申请号：US10328298
申请日：2002-12-23
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/093 , H04L7/033
摘要： In one embodiment, the present invention is directed to a system for processing a data stream. The system comprises: a voltage controlled oscillator (VCO) that generates a VCO signal in response to a tuning signal; a phase detector that generates an error signal that is indicative of a phase difference between a data signal and the VCO signal; a first filter that filters a reference signal that is indicative of an occurrence of a data transition; a second filter that filters the error signal, wherein the first filter and second filter are low-pass filters that possess a bandwidth that approximately equals one half of the reciprocal of: a unit interval multiplied by a maximum run length; and a divider circuit that divides the filtered error signal by the filtered reference signal.
摘要翻译：在一个实施例中，本发明涉及一种用于处理数据流的系统。该系统包括：压控振荡器（VCO），其响应于调谐信号产生VCO信号; 相位检测器，产生指示数据信号和VCO信号之间的相位差的误差信号; 对表示数据转换的发生的参考信号进行过滤的第一滤波器; 第二滤波器，其对所述误差信号进行滤波，其中所述第一滤波器和第二滤波器是低通滤波器，其具有大致等于以下的倒数的一半的带宽：单位间隔乘以最大游程长度; 以及除法器电路，其将滤波后的误差信号除以滤波后的参考信号。

8. 发明授权

US07106227B2 Method and apparatus for synchronizing a multiple-stage multiplexer 失效
公开(公告)号：US07106227B2
公开(公告)日：2006-09-12
申请号：US09967390
申请日：2001-09-28
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H03M9/00
CPC分类号： H04J3/047
摘要： A method and apparatus for synchronizing multiple-stage multiplexers are disclosed. According to exemplary embodiments of the present invention, multiplexer circuits in the multiple-stage multiplexer are synchronized based upon a frequency response of the output of the multiplexer. The power level of the output of the multiple-stage multiplexer is measured at a frequency corresponding to the input data rate of the multiple-stage multiplexer, during the time a test pattern is sent through the multiple-stage multiplexer. In an exemplary embodiment of the invention, the multiple-stage multiplexer is placed in substantially random states until the measured power level reaches the predetermined.

9. 发明授权

US06865345B2 Frequency translating devices and frequency translating measurement systems that utilize light-activated resistors 失效
标题翻译：使用光激活电阻的频率转换装置和频率转换测量系统
公开(公告)号：US06865345B2
公开(公告)日：2005-03-08
申请号：US09942006
申请日：2001-08-28
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： H04B10/00
CPC分类号： H04B10/806
摘要： A frequency translating device (FTD) includes at least one light-activated resistor (LAR) connected to down-convert a radio frequency (RF) to an intermediate frequency (IF) and to up-convert an IF to an RF and a source of modulated light that is optically connected to the LAR. The source of modulated light is modulated in response to a local oscillator (LO) and the LAR is activated in response to the modulated light. Modulated light can be generated from a light source and an LO by, for example, directly modulating the light source, modulating a transmission switch that blocks the transmission of light to the LAR, or modulating a light path switch. The LAR-based FTD can be used as a reciprocal FTD to characterize another FTD in a three-pair measurement system. An FTD may include more than one LAR to form, for example, single-balanced and double-balanced LAR-based FTDs.
摘要翻译：频率转换装置（FTD）包括至少一个连接到将射频（RF）下变频到中频（IF）的光启动电阻器（LAR），并将IF上变频到RF和源与LAR光学连接的调制光。响应于本地振荡器（LO）调制调制光源，并且响应于调制的光激活LAR。可以通过例如直接调制光源，调制阻挡向LAR传输光的传输开关或调制光路开关，从光源和LO生成调制光。基于LAR的FTD可以用作互逆FTD来表征三对测量系统中的另一个FTD。 FTD可以包括多于一个LAR以形成例如单平衡和双平衡LAR的FTD。

10. 发明授权

US06823466B2 Circuit and method for adjusting the clock skew in a communications system 失效
标题翻译：用于调整通信系统中的时钟偏移的电路和方法
公开(公告)号：US06823466B2
公开(公告)日：2004-11-23
申请号：US09967443
申请日：2001-09-28
申请人： Richard K. Karlquist
发明人： Richard K. Karlquist
IPC分类号： G11B500
CPC分类号： G01R31/31725 , G01R31/3191 , G01R31/31937
摘要： A circuit and method are disclosed for adjusting the clock skew in a synchronous system. The circuit and method include initially applying an offset voltage to a data input of a device in the system. Next, the clock skew between a device and a data source providing data thereto is adjusted to approximately 180 degrees, by selecting the clock skew resulting in an approximately maximum DC offset appearing at the output of the device. Thereafter, the clock skew is shifted from approximately 180 degrees to the desired clock skew amount.
摘要翻译：公开了用于调整同步系统中的时钟偏差的电路和方法。电路和方法包括首先将偏移电压施加到系统中的装置的数据输入端。接下来，通过选择时钟偏移导致出现在设备的输出处的近似最大DC偏移，将设备和提供数据的数据源之间的时钟偏差调整到大约180度。此后，时钟偏移从大约180度移动到期望的时钟偏移量。

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