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1. 发明授权

US4468684A High-density charge-coupled devices with complementary adjacent channels 失效
标题翻译：具有互补相邻通道的高密度电荷耦合器件
公开(公告)号：US4468684A
公开(公告)日：1984-08-28
申请号：US365709
申请日：1982-04-05
申请人： Leonard J. M. Esser , Ludovicus G. M. Heldens
发明人： Leonard J. M. Esser , Ludovicus G. M. Heldens
IPC分类号： G11C27/04 , H01L21/339 , H01L27/105 , H01L27/148 , H01L29/762 , H01L29/768 , H01L29/78 , G11C19/28 , H01L27/14 , H01L31/00
CPC分类号： H01L29/76858 , H01L27/1057 , H01L27/14831 , H01L29/76841 , Y10S257/912
摘要： A CCD includes several juxtaposed channels for hole transport and electron transport. Each channel forms a lateral boundary for an adjacent complementary channel so that high density in combination with a simple structure can be obtained. The CCD channels may include a matrix of photosensitive elements of a solid state image sensor for a camera. The invention may also be used in memory matrices and other CCD devices.
摘要翻译： CCD包括用于空穴传输和电子传输的几个并置通道。每个通道形成相邻互补通道的横向边界，使得可以获得与简单结构相结合的高密度。 CCD通道可以包括用于相机的固态图像传感器的感光元件的矩阵。本发明也可用于存储器矩阵和其它CCD器件。

2. 发明授权

US4234807A Ladder device with weighting factor adjusting means 失效
标题翻译：具有加权因子调节装置的梯形装置
公开(公告)号：US4234807A
公开(公告)日：1980-11-18
申请号：US885765
申请日：1978-03-13
申请人： Leonard J. M. Esser , Ludovicus G. M. Heldens
发明人： Leonard J. M. Esser , Ludovicus G. M. Heldens
IPC分类号： G11C19/00 , G11C19/28 , G11C27/00 , H01L21/339 , H01L29/762 , H01L29/78 , H03H7/30 , H03H11/26 , H03H15/02 , H03L1/00
CPC分类号： H03H15/02 , G11C19/00 , G11C27/00 , H01L29/78
摘要： A ladder device comprising at least three ladder sections connected in cascade and weighting-factor adjusting means coupled to said ladder sections and which comprises first and second field effect transistors (FET) having channel regions with different predetermined length/width ratios that define a weighting factor coefficient. A further fine adjustment of the weighting factor is achieved by adjusting the gate voltages of the FETs.
摘要翻译：一种梯形装置，包括至少三个级联连接的梯形部分和耦合到所述梯形部分的加权因子调节装置，并且包括具有不同预定长度/宽度比的沟道区的第一和第二场效应晶体管（FET），所述第一和第二场效应晶体管限定加权因子系数。通过调整FET的栅极电压，可以进一步调整加权系数。

3. 发明授权

US4677650A Charge coupled semiconductor device with dynamic control 失效
标题翻译：电荷耦合半导体器件具有动态控制
公开(公告)号：US4677650A
公开(公告)日：1987-06-30
申请号：US616936
申请日：1984-06-07
申请人： Arnoldus J. J. Boudewijns , Leonard J. M. Esser
发明人： Arnoldus J. J. Boudewijns , Leonard J. M. Esser
IPC分类号： G11C19/28 , G11C27/00 , G11C27/04 , H01L21/339 , H01L27/148 , H01L29/76 , H01L29/762 , H01L29/772 , H03H11/26 , H04N5/3725 , H04N5/376 , H04N3/14 , G11C11/40 , H01L27/10 , H01L29/78
CPC分类号： H04N3/1543 , G11C19/282 , G11C19/285 , G11C27/00 , H01L27/14831
摘要： In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.
摘要翻译：在CCD中，特别是在图像传感器装置中，通过在时钟信号和参考信号之间顺序地切换电极，信息密度可以加倍。获得时钟信号和参考信号作为由单相或多相时钟控制的移位寄存器的输出信号。例如，使用C-MOS技术提供寄存器。信号在移位寄存器的第一级的输入端与寄存器时钟的时钟脉冲信号相结合，确定移位寄存器的下一级的输出信号。因此，这些输入信号确定连接到寄存器级的输出的电极处的电压变化。

4. 发明授权

US4649554A Charge transfer device having a subdivided channel output region 失效
标题翻译：具有细分通道输出区域的电荷转移装置
公开(公告)号：US4649554A
公开(公告)日：1987-03-10
申请号：US819989
申请日：1986-01-15
申请人： Arnoldus J. J. Boudewijns , Leonard J. M. Esser
发明人： Arnoldus J. J. Boudewijns , Leonard J. M. Esser
IPC分类号： G11C19/28 , G11C27/04 , H01L21/339 , H01L29/762 , H01L29/78
CPC分类号： G11C27/04 , G11C19/285
摘要： In a charge transfer device in accordance with the invention, the channel is subdivided at the area of the output into two subchannels provided with separate output gates which are clocked in phase opposition, and with separate reset gates which are likewise clocked in phase opposition. Between the output gates and the reset gates there is arranged a floating gate common to both subchannels by which signals can be read during 100% of a clock period so that no additional filtering operations for filtering out spectra of higher order are required. This output circuit can be used in applications in which high speeds and a high sensitivity are required.
摘要翻译：在根据本发明的电荷转移装置中，通道在输出的区域被细分为两个子通道，分成两个子通道，这两个子通道具有相位相反的时钟脉冲的单独的输出门，并且具有相同时钟相位的单独的复位门。在输出门和复位门之间布置有两个子通道共用的浮动栅极，通过该浮动栅极可以在100％的时钟周期内读取信号，因此不需要用于滤除高阶光谱的附加滤波操作。该输出电路可用于需要高速度和高灵敏度的应用中。

5. 发明授权

US4586064A DMOS with high-resistivity gate electrode 失效
标题翻译：具有高电阻栅电极的DMOS
公开(公告)号：US4586064A
公开(公告)日：1986-04-29
申请号：US539446
申请日：1983-10-06
申请人： Leonard J. M. Esser , Hermanus J. H. Wilting , Eduard F. Stikvoort
发明人： Leonard J. M. Esser , Hermanus J. H. Wilting , Eduard F. Stikvoort
IPC分类号： H01L29/762 , H01L21/339 , H01L27/148 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/768 , H01L29/78 , H01L29/04 , H01L27/04
CPC分类号： H01L29/4983 , H01L29/402 , H01L29/405 , H01L29/42396 , H01L29/435 , H01L29/4916 , H01L29/76841 , H01L29/7802 , H01L29/7816 , H01L29/7835
摘要： By the use of high-resistivity polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).
摘要翻译：通过在MIS元件中使用高电阻率多晶硅（poly），可以在多晶硅材料中形成耗尽层，这导致多晶硅（gate）和下面的半导体本体之间的电去耦合。为了在衬底中获得有利的电位分布，这种效果可以有利地用于诸如CCD中的各种电路元件中。在MOS晶体管中，以减少寄生电容; 并在高电压设备中增加在场板边缘的击穿电压（resurf）。

6. 发明授权

US4903284A Accordion-type charge-coupled devices 失效
标题翻译：手风琴式电荷耦合器件
公开(公告)号：US4903284A
公开(公告)日：1990-02-20
申请号：US123697
申请日：1987-11-23
申请人： Leonard J. M. Esser
发明人： Leonard J. M. Esser
IPC分类号： G11C27/04 , H01L27/148 , H04N5/345 , H04N5/3725 , H04N5/376
CPC分类号： H04N3/1543 , G11C27/04
摘要： The invention relates to a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltages on the other hand. The electrodes are alternatively coupled to the shift register and to the clock lines. The dissipation can be considerably reduced in this device. Moreover, the transport direction can be reversed in a simple manner, which is of importance, for example, in image sensors for smear suppression.

7. 发明授权

US4730209A Circuit for converting a colour television time division multiplex signal into simultaneous signals 失效
标题翻译：用于将彩色电视时分复用信号转换成同步信号的电路
公开(公告)号：US4730209A
公开(公告)日：1988-03-08
申请号：US833632
申请日：1986-02-27
申请人： Leendert J. Van De Polder , Leonard J. M. Esser
发明人： Leendert J. Van De Polder , Leonard J. M. Esser
IPC分类号： H04N11/22 , H04N11/12
CPC分类号： H04N11/22
摘要： A color television Y/U/V luminance-chrominance multiplex signal with signals which may or may not be compressed in time comprises for a television line the associated luminance information Y and half the chrominance information U or V. As a result the circuit should supply the chrominance information directly (U, V) and repeatedly (U', V') during a subsequent television line. To avoid the use of an accurate, expensive delay device having a line period delay, the circuit includes an input shift register (A) of the series-in, parallel-out type, which is coupled through an on-off switch circuit (B1, B2) to parallel inputs of two shift registers (C1, C2) of the parallel-in, series-out type. During a line blanking period (THB) writing is effected from the input shift register in the output shift registers and during two subsequent line scan periods (THS1, THS2) reading is effected consecutively therefrom. Reading may be effected in opposite phase if a repetition is to be effected after exactly one line period.
摘要翻译：具有可能或可能不被压缩的信号的彩色电视Y / U / V亮度色度多路复用信号包括对于电视线，相关联的亮度信息Y和色度信息U或V的一半。因此，电路应该提供在随后的电视线中直接（U，V）和色度信息（U'，V'）。为了避免使用具有线路周期延迟的精确，昂贵的延迟装置，电路包括串联并联输出型的输入移位寄存器（A），其通过开 - 关开关电路（B1 ，B2）到并联串联输出类型的两个移位寄存器（C1，C2）的并行输入。在行消隐期间（THB）中，从输出移位寄存器中的输入移位寄存器进行写入，并且在两个后续行扫描周期（THS1，THS2）期间连续执行读取。如果在完全一个行周期之后进行重复，则可以在相反的阶段进行读取。

8. 发明授权

US4716446A Insulated dual gate field effect transistor 失效
标题翻译：绝缘双栅场效应晶体管
公开(公告)号：US4716446A
公开(公告)日：1987-12-29
申请号：US872630
申请日：1986-06-09
申请人： Leonard J. M. Esser , Petrus J. A. M. Van de Wiel , Leonardus A. Daverveld , Johannes A. A. Van Gils
发明人： Leonard J. M. Esser , Petrus J. A. M. Van de Wiel , Leonardus A. Daverveld , Johannes A. A. Van Gils
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/7816 , H01L21/28273 , H01L29/4916 , H01L29/66825 , H01L29/7801 , H01L29/7802 , H01L29/7831 , H01L29/7835 , H01L29/7836
摘要： A semiconductor device comprising a field effect transistor of the lateral or vertical DMOST type having a source zone of the one conductivity type, an adjoining channel region of the other conductivity type, a drain zone of the one conductivity type and a weakly doped drift region located between the drain zone and the channel region. According to the invention a second gate electrode located on the side of the drain zone and separated from the first gate electrode is disposed on the insulating layer above the channel zone behind the first gate electrode located on the side of the source zone. The length L.sub.2 of the part of the second gate electrode located above the channel zone is at least equal to that of the part of the first gate electrode located above the channel zone. As a result, a high value of the mutual conductance g.sub.m as well as good linearity can be obtained. The second gate electrode is preferably made of polycrystalline silicon,which in the operating condition is depleted at least in part above the drift region.
摘要翻译：一种半导体器件，包括具有一个导电类型的源极区，另一个导电类型的邻接沟道区，一个导电类型的漏极区和位于第一导电类型的弱掺杂漂移区的横向或垂直DMOST类型的场效应晶体管在漏区和沟道区之间。根据本发明，位于漏极区一侧并与第一栅极分离的第二栅电极设置在位于源极区一侧的第一栅电极后面的沟道区上方的绝缘层上。位于沟道区上方的第二栅电极的部分的长度L2至少等于位于沟道区上方的第一栅电极的部分的长度L2。结果，可以获得高电导gm值以及良好的线性度。第二栅电极优选由多晶硅制成，其在工作条件下至少部分地耗尽漂移区以上。

9. 发明授权

US4807005A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4807005A
公开(公告)日：1989-02-21
申请号：US254672
申请日：1981-04-16
申请人： Leonard J. M. Esser , Gijsbert Lock
发明人： Leonard J. M. Esser , Gijsbert Lock
IPC分类号： H04N5/335 , G11C19/28 , G11C27/04 , H01L21/339 , H01L27/00 , H01L27/105 , H01L27/148 , H01L29/10 , H01L29/762 , H01L29/768 , H01L27/04
CPC分类号： H01L29/1062 , G11C19/282 , G11C27/04 , H01L27/1057 , H01L29/76833
摘要： The present invention involves a semiconductor device, such as a shift register, wherein information in the form of charge carriers is moved laterally through the bulk of a semiconductor layer by means of an electric field, while the charge carriers are stored at the surface of the semiconductor layer. According to this invention, information containing regions can be separated from each other by depletion zones extending through the thickness and the width of the semiconductor layer. Charge transport laterally through the interior of the semiconductor layer results in a considerable reduction of the transport time. Majority charge carriers are advantageously used.
摘要翻译：本发明涉及诸如移位寄存器的半导体器件，其中电荷载体形式的信息通过电场横向移动穿过半导体层的主体，而电荷载体被存储在半导体层。根据本发明，包含区域的信息可以通过延伸穿过半导体层的厚度和宽度的耗尽区彼此分离。横向穿过半导体层的内部的电荷输送导致运输时间的显着降低。有利地使用多数电荷载体。

10. 发明授权

US4799109A Charge coupled sensor arrangement 失效
标题翻译：电荷耦合传感器布置
公开(公告)号：US4799109A
公开(公告)日：1989-01-17
申请号：US149981
申请日：1988-01-27
申请人： Leonard J. M. Esser , Marcellinus J. M. Pelgrom
发明人： Leonard J. M. Esser , Marcellinus J. M. Pelgrom
IPC分类号： H01L27/148 , H04N5/32 , H04N5/376 , H04N3/14
CPC分类号： H04N3/1525 , H01L27/14831
摘要： The invention relates to a charge-coupled image sensor of the line transfer type comprising a number of parallel lines (2-6) which are each constituted by an n-phase CCD. An electrode (12-16) of each CCD is arranged parallel to this CCD separately for each CCD. The other (n-1) electrodes (17-20) extend transversely to the charge transport direction over all CCD's. The first-mentioned electrode (12-16) is used as a selection gate and is moreover used, depending upon the applied voltage, as an integration gate or as a blocking gate during the integration period.
摘要翻译：本发明涉及一种线路传输类型的电荷耦合图像传感器，包括多个由n相CCD构成的平行线（2-6）。每个CCD的电极（12-16）分别平行于每个CCD的CCD。其他（n-1）个电极（17-20）横跨所有CCD的电荷输送方向延伸。首先提到的电极（12-16）用作选择栅极，并且根据所施加的电压，在积分期间作为积分栅极或阻挡栅极使用。

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