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1. 发明授权

US08043888B2 Phase change memory cell with heater and method therefor 有权
标题翻译：具有加热器的相变存储器单元及其方法
公开(公告)号：US08043888B2
公开(公告)日：2011-10-25
申请号：US12016733
申请日：2008-01-18
申请人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
发明人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
IPC分类号： H01L21/44
CPC分类号： H01L45/1675 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144
摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
摘要翻译：形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

2. 发明授权

US07192876B2 Transistor with independent gate structures 有权
标题翻译：具有独立门结构的晶体管
公开(公告)号：US07192876B2
公开(公告)日：2007-03-20
申请号：US10443375
申请日：2003-05-22
申请人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
IPC分类号： H01L21/308
CPC分类号： H01L29/785 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/66818 , H01L29/7881 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.
摘要翻译：制造具有独立栅极结构的晶体管的方法。栅极结构各自与半导体结构的侧壁相邻。该方法包括在包括沟道区域的半导体结构上沉积包括栅极材料层的至少一个共形层。在晶片上形成平面层。平面层在衬底上方的位置处具有在大致最小一个共形层的顶表面下方的顶表面。蚀刻至少一个共形层以去除半导体结构上的栅极材料。

3. 发明申请

US20060197140A1 Vertical transistor NVM with body contact structure and method 审中-公开
标题翻译：垂直晶体管NVM具有体接触结构和方法
公开(公告)号：US20060197140A1
公开(公告)日：2006-09-07
申请号：US11072878
申请日：2005-03-04
申请人： Ramachandran Muralidhar , Yang Du , Leo Mathew
发明人： Ramachandran Muralidhar , Yang Du , Leo Mathew
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device (151) is provided which comprises (a) a semiconductor substrate (103); (b) a fin (109) comprising a semiconductor material and being in electrical contact with the substrate; (c) a first floating gate (121) disposed on a first side of said fin; and (d) a control gate (107).
摘要翻译：提供半导体器件（151），其包括（a）半导体衬底（103）; （b）包括半导体材料并与基底电接触的翅片（109）; （c）设置在所述散热片的第一侧上的第一浮动栅极（121）和（d）控制门（107）。

4. 发明申请

US20050124130A1 Semiconductor fabrication process with asymmetrical conductive spacers 有权
标题翻译：具有不对称导电间隔物的半导体制造工艺
公开(公告)号：US20050124130A1
公开(公告)日：2005-06-09
申请号：US11036860
申请日：2005-01-13
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.
摘要翻译：半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调整通道植入物的需要。

5. 发明授权

US06831310B1 Integrated circuit having multiple memory types and method of formation 失效
标题翻译：具有多种存储器类型和形成方法的集成电路
公开(公告)号：US06831310B1
公开(公告)日：2004-12-14
申请号：US10705504
申请日：2003-11-10
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L2980
CPC分类号： H01L27/108 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/785 , H01L29/7881
摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.
摘要翻译：晶体管（10）形成有三个可分别控制的栅极（44,42,18）。三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。通道侧壁上的电介质可以不同于通道顶部的电介质。选择性地制造到源极，漏极和三个栅极的电接触。通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

6. 发明授权

US07098502B2 Transistor having three electrically isolated electrodes and method of formation 有权
标题翻译：具有三个电隔离电极的晶体管和形成方法
公开(公告)号：US07098502B2
公开(公告)日：2006-08-29
申请号：US10705317
申请日：2003-11-10
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L27/108 , H01L27/12 , H01L21/00 , H01L21/336
CPC分类号： H01L27/108 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881
摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.
摘要翻译：晶体管（10）形成有三个可分别控制的栅极（44,42,18）。三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。通道侧壁上的电介质可以不同于通道顶部的电介质。选择性地制造到源极，漏极和三个栅极的电接触。通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

7. 发明授权

US07018876B2 Transistor with vertical dielectric structure 有权
标题翻译：具有垂直电介质结构的晶体管
公开(公告)号：US07018876B2
公开(公告)日：2006-03-28
申请号：US10871772
申请日：2004-06-18
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/66795 , H01L29/66825 , H01L29/785 , H01L29/7887
摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.
摘要翻译：一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。半导体结构包括沟道区（731）和源极/漏极区（707,709）。晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。

8. 发明授权

US06903967B2 Memory with charge storage locations and adjacent gate structures 有权
标题翻译：具有电荷存储位置和相邻门结构的存储器
公开(公告)号：US06903967B2
公开(公告)日：2005-06-07
申请号：US10443908
申请日：2003-05-22
申请人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L29/66818 , H01L29/66825 , H01L29/785 , H01L29/7855 , H01L29/7887 , H01L29/7923
摘要： A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.
摘要翻译：一种存储器，其具有邻近半导体结构的相对侧壁的栅极结构，该半导体结构包括沟道区和栅极结构与相对侧壁之间的多个电荷存储位置。沟道区域位于两个电流端子区域之间，在一个示例中，该区域用作源极/漏极区域。存储器单元可以在存储单元的阵列中实现，其中一个栅极结构耦合到一个字线，而另一个栅极结构耦合到另一个字线。在一个示例中，每个单元包括四个电荷存储位置，每个用于存储一位数据。

9. 发明申请

US20050057964A1 MEMORY WITH CHARGE STORAGE LOCATIONS AND ADJACENT GATE STRUCTURES 有权
标题翻译：具有充电储存位置和相似门结构的存储器
公开(公告)号：US20050057964A1
公开(公告)日：2005-03-17
申请号：US10443908
申请日：2003-05-22
申请人： Leo Mathew , Robert Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert Steimle , Ramachandran Muralidhar
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L29/66818 , H01L29/66825 , H01L29/785 , H01L29/7855 , H01L29/7887 , H01L29/7923
摘要： A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.
摘要翻译：一种存储器，其具有邻近半导体结构的相对侧壁的栅极结构，该半导体结构包括沟道区和栅极结构与相对侧壁之间的多个电荷存储位置。沟道区域位于两个电流端子区域之间，在一个示例中，该区域用作源极/漏极区域。存储器单元可以在存储单元的阵列中实现，其中一个栅极结构耦合到一个字线，而另一个栅极结构耦合到另一个字线。在一个示例中，每个单元包括四个电荷存储位置，每个用于存储一位数据。

10. 发明申请

US20090184309A1 PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR 有权
标题翻译：相变存储器与加热器及其方法
公开(公告)号：US20090184309A1
公开(公告)日：2009-07-23
申请号：US12016733
申请日：2008-01-18
申请人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
发明人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144
摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
摘要翻译：形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

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