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1. 发明申请

US20090219752A1 Apparatus and Method for Improving Storage Latch Susceptibility to Single Event Upsets 审中-公开
标题翻译：改善单个事件颠簸的存储锁定敏感性的装置和方法
公开(公告)号：US20090219752A1
公开(公告)日：2009-09-03
申请号：US12039119
申请日：2008-02-28
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C11/413 , H03K19/003
CPC分类号： G11C11/4125 , G11C11/413 , H03K3/0375
摘要： An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state circuit coupled to separate data nodes within the DICE latch; and a pair of local clock circuits configured within the storage latch circuit, the pair of local clock circuits configured to generate a duplicate pair of control signals that separately control a corresponding one of the separate three-state circuits. In the event of a charge accumulation event on only one of the pair of local clock circuits so as to change the logical state of the corresponding control signal, the presence of the other of the pair of local clock circuits that remains unaffected by the charge accumulation event prevents an error in the logical state of the DICE latch.
摘要翻译：一种用于改善对单个事件扰乱的存储锁存敏感性的装置包括配置在存储锁存电路内的双互连存储单元（DICE）; 配置为写入DICE锁存器的一对分离的三态电路，其中每个三态电路耦合到DICE锁存器内的单独的数据节点; 以及配置在所述存储锁存电路内的一对本地时钟电路，所述一对本地时钟电路经配置以产生分别控制所述分离的三态电路中对应的一个的一对控制信号。在仅一对本地时钟电路中的一个电荷累积事件的情况下，为了改变对应的控制信号的逻辑状态，保持不受电荷累积影响的一对本地时钟电路中的另一个的存在事件防止DICE锁存器的逻辑状态中的错误。

2. 发明申请

US20060044049A1 LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME 有权
标题翻译：具有差分感应方案的低电压可编程电源
公开(公告)号：US20060044049A1
公开(公告)日：2006-03-02
申请号：US10711205
申请日：2004-09-01
申请人： Michael Ouellette , Larry Wissel
发明人： Michael Ouellette , Larry Wissel
IPC分类号： H01H37/76
CPC分类号： G11C29/027 , G11C17/14 , G11C17/16 , G11C17/18 , G11C29/02 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.
摘要翻译：公开了一种用于低电压编程的集成电路的电子熔丝结构，并结合了差分感测方案。在Vdd执行感测操作时，以大约1.5倍的Vdd执行编程步骤，这限制了由感测操作引起的电子熔断器的电阻变化。在感测操作期间，门控晶体管模拟保险丝选择晶体管上的电压降，用于完整的熔丝的情况。还公开了用于表征电子熔断器的电阻的电路和方法。

3. 发明授权

US06426641B1 Single pin performance screen ring oscillator with frequency division 失效
标题翻译：单针性能屏幕振荡器分频
公开(公告)号：US06426641B1
公开(公告)日：2002-07-30
申请号：US09177139
申请日：1998-10-21
申请人： Steven P. Koch , Donald L. Wheater , Larry Wissel
发明人： Steven P. Koch , Donald L. Wheater , Larry Wissel
IPC分类号： G01R3128
CPC分类号： G01R31/2882
摘要： An oscillator circuit on a chip with a single I/O node whose output generally corresponds to a performance level of the IC chip. The single I/O node provides an easy access and testing point for evaluating chip performance. The I/O node is used for coupling to the oscillator circuit, and for activating and monitoring its oscillating output signal. The single I/O node may be accessed at the wafer level, after packaging, or in the field.
摘要翻译：具有单个I / O节点的芯片上的振荡器电路，其输出通常对应于IC芯片的性能水平。单个I / O节点提供了一个易于访问和测试点来评估芯片性能。 I / O节点用于耦合到振荡器电路，并用于激活和监视其振荡输出信号。单个I / O节点可以在晶片级，封装之后或现场访问。

4. 发明授权

US07826285B2 Memory column redundancy scheme 失效
标题翻译：内存列冗余方案
公开(公告)号：US07826285B2
公开(公告)日：2010-11-02
申请号：US11853892
申请日：2007-09-12
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C29/00
CPC分类号： G11C29/848 , G11C29/846
摘要： A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
摘要翻译：提供了一种用于实现存储器列冗余方案的系统。该系统包括具有多个列的核心阵列和冗余列，每个冗余列被配置用于读取或写入用于转向磁芯阵列中的有缺陷的列的信息和电路的位，其中电路包括一个列多路复用器，其导致具有存储器列冗余方案包括一个复用级。

5. 发明授权

US07315193B2 Circuitry and method for programming an electrically programmable fuse 失效
标题翻译：用于编程电可编程保险丝的电路和方法
公开(公告)号：US07315193B2
公开(公告)日：2008-01-01
申请号：US11161966
申请日：2005-08-24
申请人： Darren L. Anand , Larry Wissel
发明人： Darren L. Anand , Larry Wissel
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.
摘要翻译：电路包括用于提供用于控制编程晶体管（212）的栅极的可变栅极信号（220）的电压控制器（224），其与编程集成电路的电可编程熔丝（“eFuse”）（204）一起使用（200）。电压控制器根据电路是否处于eFuse编程模式或eFuse电阻测量模式来调节门信号。电压控制器可以可选地包括用于调谐门信号的电压调谐器（252），以解决由制造变化引起的编程晶体管的工作变化。

6. 发明申请

US20070046361A1 CIRCUITRY AND METHOD FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE FUSE 失效
标题翻译：用于编程电可编程保险丝的电路和方法
公开(公告)号：US20070046361A1
公开(公告)日：2007-03-01
申请号：US11161966
申请日：2005-08-24
申请人： Darren Anand , Larry Wissel
发明人： Darren Anand , Larry Wissel
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.
摘要翻译：电路包括用于提供用于控制编程晶体管（212）的栅极的可变栅极信号（220）的电压控制器（224），其与编程集成电路的电可编程熔丝（“eFuse”）（204）一起使用（200）。电压控制器根据电路是否处于eFuse编程模式或eFuse电阻测量模式来调节门信号。电压控制器可以可选地包括用于调谐门信号的电压调谐器（252），以解决由制造变化引起的编程晶体管的工作变化。

7. 发明授权

US06490708B2 Method of integrated circuit design by selection of noise tolerant gates 失效
公开(公告)号：US06490708B2
公开(公告)日：2002-12-03
申请号：US09812211
申请日：2001-03-19
申请人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
发明人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
IPC分类号： G06E1750
CPC分类号： G06F17/505
摘要： A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

8. 发明授权

US08619979B2 Physically unclonable function implemented through threshold voltage comparison 失效
标题翻译：通过阈值电压比较实现物理不可克隆功能
公开(公告)号：US08619979B2
公开(公告)日：2013-12-31
申请号：US12823278
申请日：2010-06-25
申请人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
发明人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
IPC分类号： G06F21/73 , H04L9/08
CPC分类号： G06F21/73 , H04L9/08 , H04L9/0866 , H04L9/3278
摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.
摘要翻译：公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。在特定实施例中，电子设备可操作以产生对挑战的响应。电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。电子设备包括被配置为接收挑战的挑战输入。挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

9. 发明申请

US20110317829A1 Physically Unclonable Function Implemented Through Threshold Voltage Comparison 失效
标题翻译：通过阈值电压比较实现的物理不可克隆功能
公开(公告)号：US20110317829A1
公开(公告)日：2011-12-29
申请号：US12823278
申请日：2010-06-25
申请人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
发明人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
IPC分类号： H04L9/20
CPC分类号： G06F21/73 , H04L9/08 , H04L9/0866 , H04L9/3278
摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.
摘要翻译：公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。在特定实施例中，电子设备可操作以产生对挑战的响应。电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。电子设备包括被配置为接收挑战的挑战输入。挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

10. 发明申请

US20090067269A1 MEMORY COLUMN REDUNDANCY SCHEME 失效
标题翻译：记忆库冗余计划
公开(公告)号：US20090067269A1
公开(公告)日：2009-03-12
申请号：US11853892
申请日：2007-09-12
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C29/00
CPC分类号： G11C29/848 , G11C29/846
摘要： A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
摘要翻译：提供了一种用于实现存储器列冗余方案的系统。该系统包括具有多个列的核心阵列和冗余列，每个冗余列被配置用于读取或写入用于转向磁芯阵列中的有缺陷的列的信息和电路的位，其中电路包括一个列多路复用器，其导致具有存储器列冗余方案包括一个复用级。

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