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1. 发明授权

US09197225B2 Control voltage mirror circuit 有权
标题翻译：控制电压镜电路
公开(公告)号：US09197225B2
公开(公告)日：2015-11-24
申请号：US13253395
申请日：2011-10-05
申请人： Kennedy K. Cheruiyot , Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom
发明人： Kennedy K. Cheruiyot , Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom
IPC分类号： G06F17/50 , H03L7/093
CPC分类号： H03L7/093 , G06F17/5063
摘要： A circuit for implementing a control voltage mirror is provided. A filter includes a filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier having a positive input connected to the control voltage, and a negative input is connected to an output and coupled to the distal side of the capacitor. Voltage across the capacitor is held to be near or at zero volts, substantially eliminating capacitor leakage current.
摘要翻译：提供实现控制电压反射镜的电路。滤波器包括连接到控制电压的滤波电容器和连接到电压基准的电容器的远侧。控制电压反射镜包括具有连接到控制电压的正输入的运算放大器，负输入连接到输出并耦合到电容器的远侧。电容器两端的电压保持接近或零伏，基本上消除了电容器漏电流。

2. 发明申请

US20120212280A1 IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL 有权
标题翻译：用自动模式控制实现双速水平调节
公开(公告)号：US20120212280A1
公开(公告)日：2012-08-23
申请号：US13030516
申请日：2011-02-18
申请人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
发明人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
IPC分类号： H03L5/00 , G06F17/50
CPC分类号： H03L7/085 , H03L7/083 , H03L7/099 , H03L7/18
摘要： A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.
摘要翻译：一种用于实现具有自动模式控制的双速电平转换器的方法和电路，以及设置有该电路所在的设计结构。使用低速电平移位器和高速电平移位器来提供宽的频率范围的操作。电路工作在低速模式或高速模式之一。通过检测要进行电平移位的信号的频率，自动选择适当的模式。当输入信号比参考频率慢时，选择低速电平移位器，当输入信号比参考频率快时，选择高速电平转换器。

3. 发明授权

US08237510B2 Implementing phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock 有权
标题翻译：通过宽范围的动态参考时钟实现具有增强锁定能力的锁相环（PLL）
公开(公告)号：US08237510B2
公开(公告)日：2012-08-07
申请号：US12858881
申请日：2010-08-18
申请人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
发明人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
IPC分类号： H03L7/085 , H03L7/089
CPC分类号： H03L7/099 , H03L7/103
摘要： A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.
摘要翻译：一种用于实现具有宽范围动态参考时钟的增强锁定能力的方法和锁相环（PLL）电路，以及设置有被摄体电路所在的设计结构。 PLL电路包括压控振荡器（VCO）和接收差分滤波器VCO控制电压的多个滤波器比较器。比较差分滤波器VCO控制电压值的多个滤波器比较器根据比较的差分滤波器VCO控制电压值提供相应的门控使能信号。响应于相应的门使能信号和宽范围动态参考时钟，时钟信号被施加到向上/向下计数器。将向上/向下计数器的计数值提供给VCO以选择VCO的相应频率范围。

4. 发明申请

US20120194236A1 IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK 审中-公开
标题翻译：通过宽范围动态参考时钟实现具有增强锁定能力的锁相环（PLL）
公开(公告)号：US20120194236A1
公开(公告)日：2012-08-02
申请号：US13444633
申请日：2012-04-11
申请人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
发明人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
IPC分类号： H03L7/08 , G06F17/50
CPC分类号： H03L7/099 , H03L7/103
摘要： A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.
摘要翻译：一种用于实现具有宽范围动态参考时钟的增强锁定能力的方法和锁相环（PLL）电路，以及设置有被摄体电路所在的设计结构。 PLL电路包括压控振荡器（VCO）和接收差分滤波器VCO控制电压的多个滤波器比较器。比较差分滤波器VCO控制电压值的多个滤波器比较器根据比较的差分滤波器VCO控制电压值提供相应的门控使能信号。响应于相应的门使能信号和宽范围动态参考时钟，时钟信号被施加到向上/向下计数器。将向上/向下计数器的计数值提供给VCO以选择VCO的相应频率范围。

5. 发明授权

US08751982B2 Implementing dual speed level shifter with automatic mode control 有权
标题翻译：实现具有自动模式控制的双速电平转换器
公开(公告)号：US08751982B2
公开(公告)日：2014-06-10
申请号：US13602164
申请日：2012-09-02
申请人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
发明人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
IPC分类号： G06F9/45
CPC分类号： H03L7/085 , H03L7/083 , H03L7/099 , H03L7/18
摘要： A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.
摘要翻译：一种用于实现具有自动模式控制的双速电平转换器的方法和电路，以及设置有该电路所在的设计结构。使用低速电平移位器和高速电平移位器来提供宽的频率范围的操作。电路工作在低速模式或高速模式之一。通过检测要进行电平移位的信号的频率，自动选择适当的模式。当输入信号比参考频率慢时，选择低速电平移位器，当输入信号比参考频率快时，选择高速电平转换器。

6. 发明申请

US20130106461A1 IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF) 有权
标题翻译：实现单个不同功能（PUF）场效应比较的屏幕
公开(公告)号：US20130106461A1
公开(公告)日：2013-05-02
申请号：US13284239
申请日：2011-10-28
申请人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
发明人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： G06F7/588 , H04L9/3278
摘要： A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.
摘要翻译：一种用于实现物理不可克隆功能（PUF）的屏蔽方法和电路，以及提供主题电路所在的设计结构。多个场效应晶体管（FET）耦合到低偏移动态比较器，并且分别被选择以提供多个FET对。对于每个FET对，识别并记录获得比较器输出转换的电压偏移。将每个FET对的记录电压偏移与余量阈值进行比较。对于PUF响应生成使用，具有小于边缘阈值的识别的电压偏移的每个FET对被丢弃或禁用。

7. 发明申请

US20120331432A1 IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL 有权
公开(公告)号：US20120331432A1
公开(公告)日：2012-12-27
申请号：US13602164
申请日：2012-09-02
申请人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
发明人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
IPC分类号： G06F17/50
CPC分类号： H03L7/085 , H03L7/083 , H03L7/099 , H03L7/18
摘要： A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

8. 发明授权

US08324933B2 Implementing dual speed level shifter with automatic mode control 有权
标题翻译：实现具有自动模式控制的双速电平转换器
公开(公告)号：US08324933B2
公开(公告)日：2012-12-04
申请号：US13030516
申请日：2011-02-18
申请人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
发明人： Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom , Jianguo Yao
IPC分类号： H03K19/0175
CPC分类号： H03L7/085 , H03L7/083 , H03L7/099 , H03L7/18
摘要： A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.
摘要翻译：一种用于实现具有自动模式控制的双速电平转换器的方法和电路，以及设置有该电路所在的设计结构。使用低速电平移位器和高速电平移位器来提供宽的频率范围的操作。电路工作在低速模式或高速模式之一。通过检测要进行电平移位的信号的频率，自动选择适当的模式。当输入信号比参考频率慢时，选择低速电平移位器，当输入信号比参考频率快时，选择高速电平转换器。

9. 发明申请

US20120047481A1 IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK 有权
公开(公告)号：US20120047481A1
公开(公告)日：2012-02-23
申请号：US12858881
申请日：2010-08-18
申请人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
发明人： Joel T. Ficke , Grant P. Kesselring , James D. Strom
IPC分类号： G06F17/50 , H03L7/08
CPC分类号： H03L7/099 , H03L7/103
摘要： A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

10. 发明申请

US20110298474A1 IMPLEMENTING INTEGRAL DYNAMIC VOLTAGE SENSING AND TRIGGER 失效
标题翻译：实现一体化动态电压传感和触发
公开(公告)号：US20110298474A1
公开(公告)日：2011-12-08
申请号：US12792160
申请日：2010-06-02
申请人： Kennedy K. Cheruiyot , Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom
发明人： Kennedy K. Cheruiyot , Joel T. Ficke , David M. Friend , Grant P. Kesselring , James D. Strom
IPC分类号： G01R29/26
CPC分类号： G01R29/26
摘要： A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.
摘要翻译：一种用于实现动态电压感测和触发电路的方法和电路，以及提供对象电路所在的设计结构。电压感测电路包括产生参考时钟的第一安静振荡器和产生噪声时钟的第二噪声振荡器。耦合到第一安静振荡器和第二噪声振荡器的数字控制回路匹配第一安静振荡器和第二噪声振荡器的频率。参考时钟驱动第一预定义位移位寄存器，并且噪声时钟驱动第二预定义位移位寄存器，其中第二预定义位移位寄存器大于第一预定义位移位寄存器。当第一预定义位移位寄存器溢出时，第二预定义位移位寄存器的内容被评估。将第二预定义位移位寄存器的内容与噪声阈值选择值进行比较，以识别噪声事件并触发噪声检测器控制输出。

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