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1. 发明授权

US5880979A System for providing the absolute difference of unsigned values 失效
标题翻译：用于提供无符号值的绝对差的系统
公开(公告)号：US5880979A
公开(公告)日：1999-03-09
申请号：US576469
申请日：1995-12-21
申请人： Larry M. Mennemeier , Alexander D. Peleg , Koby Gottlieb
发明人： Larry M. Mennemeier , Alexander D. Peleg , Koby Gottlieb
IPC分类号： G06F7/544 , G06F9/302 , G06F7/00 , G06F7/38
CPC分类号： G06F9/30014 , G06F17/10 , G06F7/544 , G06F9/30036 , G06F2207/5442
摘要： In a computer system storing a first packed data and a second packed data having corresponding data elements where the data elements representing unsigned values having a system for determining the absolute difference of the corresponding data elements. The system comprising the steps of subtracting with saturation the data elements in the first packed data from the corresponding data elements in the second packed data to generate a third packed data in response to a first instruction, subtracting with saturation the data elements in the second packed data from the corresponding data elements in the first packed data to generate a fourth packed data in response to a second instruction and performing an operation to select the data elements of the third packed data and the fourth packed data of greatest value to generate a fifth packed data in response to a third instruction.
摘要翻译：在存储第一打包数据的计算机系统和具有相应数据元素的第二打包数据中，其中表示无符号值的数据元素具有用于确定相应数据元素的绝对差的系统。该系统包括以下步骤：饱和地从第二打包数据中的相应数据元素中减去第一打包数据中的数据元素，以响应于第一指令产生第三打包数据，以饱和度减去第二打包数据中的数据元素来自第一打包数据中的相应数据元素的数据，以响应于第二指令生成第四打包数据，并且执行选择第三打包数据的数据元素和最大值的第四打包数据的操作以生成第五打包响应于第三条指令的数据。

2. 发明申请

US20120216018A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20120216018A1
公开(公告)日：2012-08-23
申请号：US13456761
申请日：2012-04-26
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

3. 发明授权

US07509367B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07509367B2
公开(公告)日：2009-03-24
申请号：US10861167
申请日：2004-06-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

4. 发明授权

US07480686B2 Method and apparatus for executing packed shift operations 有权
标题翻译：用于执行打包移位操作的方法和装置
公开(公告)号：US07480686B2
公开(公告)日：2009-01-20
申请号：US10846726
申请日：2004-05-14
申请人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
发明人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
IPC分类号： G06F5/01
CPC分类号： G06F7/762 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.
摘要翻译：一种用于对具有多个值的压缩数据元素执行移位操作的方法和装置。一个实施例包括从存储器访问第一格式的移位控制信号。移位控制信号识别第一打包移位操作以及移位位置是字节位置还是位位置，并使处理器执行一组第二格式的控制信号，从而访问打包数据，将打包数据移位根据第一打包移位操作的移位位置的数量，产生用于多个位置之一的第一替换数据，并且产生包括第一替换数据的移位的第一打包数据。

5. 发明授权

US07451169B2 Method and apparatus for providing packed shift operations in a processor 失效
标题翻译：用于在处理器中提供打包移位操作的方法和装置
公开(公告)号：US07451169B2
公开(公告)日：2008-11-11
申请号：US11454749
申请日：2006-06-15
申请人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F5/01
CPC分类号： G06F7/762 , G06F5/01 , G06F7/49994 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3885
摘要： A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
摘要翻译：一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。每个输出对应于移位包装结果的一位。

6. 发明授权

US06738793B2 Processor capable of executing packed shift operations 失效
标题翻译：能够执行打包移位操作的处理器
公开(公告)号：US06738793B2
公开(公告)日：2004-05-18
申请号：US09783816
申请日：2001-02-14
申请人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
发明人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
IPC分类号： G06F505
CPC分类号： G06F7/762 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
摘要翻译：一种用于对具有多个值的压缩数据元素执行移位操作的装置。所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。每个输出对应于移位包装结果的一位。

7. 发明授权

US06385634B1 Method for performing multiply-add operations on packed data 失效
标题翻译：对打包数据进行乘法运算的方法
公开(公告)号：US06385634B1
公开(公告)日：2002-05-07
申请号：US08522067
申请日：1995-08-31
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F738
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

8. 发明授权

US5835392A Method for performing complex fast fourier transforms (FFT's) 失效
标题翻译：执行复杂快速傅立叶变换（FFT）的方法
公开(公告)号：US5835392A
公开(公告)日：1998-11-10
申请号：US580467
申请日：1995-12-28
申请人： Carole Dulong , Larry M. Mennemeier , Eiichi Kowashi , Alexander D. Peleg , Stephen A. Fischer
发明人： Carole Dulong , Larry M. Mennemeier , Eiichi Kowashi , Alexander D. Peleg , Stephen A. Fischer
IPC分类号： G06F17/14 , G06F15/00 , G06F7/38
CPC分类号： G06F17/142 , G06F9/3001 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method in a computer system of performing a butterfly stage of a complex fast fourier transform of two input signals. First, a packed multiply add is performed on a first packed complex value generated from a first input signal and a set of trigonometric values to generate a first product. Then, a second product is generated which comprises the first product with a sign inverted. A packed add of the second product and a second complex value generated from a second input signal is performed to generate a first result, and the first product and the second complex value to generate a second result.
摘要翻译：一种执行两个输入信号的复杂快速傅里叶变换的蝶形阶段的计算机系统中的方法。首先，对从第一输入信号和一组三角值生成的第一打包复数值执行打包乘法加法，以生成第一乘积。然后，产生第二产品，其包括具有倒牌的第一产品。执行第二产品的打包添加和从第二输入信号产生的第二复数值以产生第一结果，以及第一乘积和第二复数值以产生第二结果。

9. 发明申请

US20120331028A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
标题翻译：用于在包装数据上执行多重添加操作的处理器
公开(公告)号：US20120331028A1
公开(公告)日：2012-12-27
申请号：US13603370
申请日：2012-09-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

10. 发明授权

US08185571B2 Processor for performing multiply-add operations on packed data 有权
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08185571B2
公开(公告)日：2012-05-22
申请号：US12409275
申请日：2009-03-23
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

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