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1. 发明授权

US07468974B1 Efficient strictly non-blocking multicast switch architecture for time division multiplexed traffic 失效
标题翻译：高效的严格无阻塞的组播交换机架构，用于时分复用业务
公开(公告)号：US07468974B1
公开(公告)日：2008-12-23
申请号：US10946178
申请日：2004-09-22
申请人： Larrie Simon Carr , Winston Ki-Cheong Mok , Kenneth Evert Sailor
发明人： Larrie Simon Carr , Winston Ki-Cheong Mok , Kenneth Evert Sailor
IPC分类号： H04Q11/00
CPC分类号： H04Q3/545 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13056 , H04Q2213/13103 , H04Q2213/13166 , H04Q2213/13242 , H04Q2213/13292 , H04Q2213/1334
摘要： A Forward Propagation Architecture is a novel switch architecture based on well-known unicast switching architectures, and provides two desirable properties: (1) no rearrangement of established calls is ever required and (2) the architecture is strictly non-blocking for multicast, even when multicast destinations are dynamically added to existing calls. These properties (excluding dynamic multicast destination addition) can be provided by standard architectures or Time:Space:Time architectures with speedup proportional to the width of the widest multicast to be supported. The speedup required by the FPA is constant and practical (approximately 4× speedup) and at significantly less hardware cost than n2 architectures. The key to the FPA's capability is a sequentially doubled fabric with a feedback loop. The FPA requires a routing algorithm for connection setting. The connection-setting algorithm is sufficiently simple to be implemented in hardware.
摘要翻译：前向传播体系结构是一种基于众所周知的单播交换架构的新型交换机架构，提供了两个理想的特性：（1）不需要重新建立已建立的呼叫，（2）架构严格无阻塞组播，甚至当多播目的地动态添加到现有呼叫时。这些属性（不包括动态组播目的地添加）可以由标准架构或Time：Space：Time架构提供，加速与要支持的最宽广的多播的宽度成比例。 FPA所需的加速是恒定和实用的（约4倍加速），并且比n2架构显着降低硬件成本。 FPA的能力的关键是依次加倍的织物与反馈回路。 FPA需要用于连接设置的路由算法。连接设置算法足够简单，可以在硬件中实现。

2. 发明授权

US06333935B1 State machine architecture with multiplexed random access memory 失效
标题翻译：具有复用随机存取存储器的状态机架构
公开(公告)号：US06333935B1
公开(公告)日：2001-12-25
申请号：US09057509
申请日：1998-04-09
申请人： Larrie Simon Carr , Winston Ki-Cheong Mok
发明人： Larrie Simon Carr , Winston Ki-Cheong Mok
IPC分类号： H04B7212
CPC分类号： G06F7/00 , H04J3/047
摘要： A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof. A null cycle generator coupled to the pipeline and to the controller inserts null cycles into the concurrently processed data streams at regular time intervals and outputs a NULL signal to the controller during each null cycle. A multiplexer coupled between the controller and the memory multiplexes access to the memory between the controller/pipeline, and an alternate controller. Read access to the memory by the controller or pipeline is inhibited while the NULL signal is output, and write access to the memory by the pipeline is inhibited while an OUTGOING NULL replica of the NULL signal is being output by the pipeline during the final clock cycle. Accordingly, the alternate controller may gain read access to the memory while the NULL signal is output, and may gain write access to the memory while the OUTGOING NULL signal is output.
摘要翻译：被并入包含多个数据字并由状态向量表征的单个数据流的多个时分复用数据流被同时处理。状态向量存储在具有多个可寻址存储器位置的读写存储器中。在初始时钟周期期间，流水线从数据流之一接收输入数据字，表征该数据流的输入状态向量和输入状态向量的存储器位置地址。在一个或多个中间时钟周期期间，流水线处理输入数据字和输入状态向量以产生输出数据字和输出状态向量。在最后的时钟周期期间，流水线将输出数据字传送到输出数据流，并将输出状态向量传送到上述存储位置地址。耦合到存储器和管线的控制器同步其操作。耦合到流水线和控制器的零周期发生器以固定的时间间隔将空周期插入到并行处理的数据流中，并且在每个空循环期间向控制器输出空信号。耦合在控制器和存储器之间的复用器多路复用对控制器/流水线与备用控制器之间的存储器的访问。当输出NULL信号时，控制器或流水线读取存储器的访问被禁止，并且在最终时钟周期期间管道输出NULL信号的OUTGOING NULL复制品时，流水线对存储器的写访问被禁止。因此，当输出NULL信号时，备用控制器可以获得对存储器的读取访问，并且可以在输出OUTGOING NULL信号时获得对存储器的写访问。

3. 发明授权

US06188699B1 Multi-channel encoder/decoder 失效
标题翻译：多通道编码器/解码器
公开(公告)号：US06188699B1
公开(公告)日：2001-02-13
申请号：US08989162
申请日：1997-12-11
申请人： Steven Forbes Lang , Winston Ki-Cheong Mok , Larrie Simon Carr , Richard Arthur John Steedman , Glenn Kenneth Bindley
发明人： Steven Forbes Lang , Winston Ki-Cheong Mok , Larrie Simon Carr , Richard Arthur John Steedman , Glenn Kenneth Bindley
IPC分类号： H04J302
CPC分类号： H04L29/06 , H04L69/14
摘要： A multi-channel network device for interfacing between a plurality of physical data links and a control processor, where each physical data link is characterized by a data stream of data packets communicated according to a data link control protocol. The multi-channel network device includes a plurality of receive-side line interfaces, with each with each receive-side line interface having at least one channel associated therewith. Each receive-side line interface is operative to receive incoming data packets from one of the physical data links such that each incoming data packet is received in at least one incoming data segment. Each receive-side line interface is also operative to determine a time-slot number for each incoming data segment arriving thereon.
摘要翻译：一种多通道网络设备，用于在多个物理数据链路和控制处理器之间进行接口，其中每个物理数据链路的特征在于根据数据链路控制协议传送的数据分组的数据流。多通道网络设备包括多个接收侧线路接口，每个接收侧线路接口具有与其相关联的至少一个信道。每个接收侧线路接口可操作以从物理数据链路之一接收输入数据分组，使得每个输入数据分组在至少一个输入数据分段中被接收。每个接收侧线接口还可操作以确定到达其上的每个输入数据段的时隙号。

4. 发明授权

US08428203B1 Integrated tunable RF notch filter 有权
标题翻译：集成可调RF陷波滤波器
公开(公告)号：US08428203B1
公开(公告)日：2013-04-23
申请号：US12349328
申请日：2009-01-06
申请人： Anthony Eugene Zortea , Mathew McAdam , Mathieu Gagnon , Graeme Boyd , Winston Ki-Cheong Mok
发明人： Anthony Eugene Zortea , Mathew McAdam , Mathieu Gagnon , Graeme Boyd , Winston Ki-Cheong Mok
IPC分类号： H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08
CPC分类号： H04B1/1036 , H03H11/10
摘要： Large interfering signals (interferers) with spectra near a desired signal can cause distortion in a wireless receiver due to a non-linear signal path. It is typically a performance advantage to attenuate these interferers earlier in the signal path, rather than later in the signal path, because these interferers can cause saturation of amplifying stages. In certain situations, the frequency offset of an interfering signal, with respect to the desired signal, can be on the order of 10 megahertz (MHz), whereas the center frequencies can be on the order of several gigahertz (GHz). Thus, a filter with “baseband” precision would be needed at radio frequency to notch out the interferer, which is relatively difficult to do. Disclosed is a technique to estimate the relative strength and center frequency of the interferer and to place the center frequency of a notch filter adaptively and precisely at the interferer location.
摘要翻译：具有靠近所需信号的频谱的大干扰信号（干扰源）可能由于非线性信号路径而导致无线接收机中的失真。通常在信号路径中更早地衰减这些干扰源，而不是在信号路径的后期衰减这些性能优势，因为这些干扰源可能导致放大级的饱和。在某些情况下，相对于所需信号，干扰信号的频偏可以在10兆赫兹（MHz）的数量级上，而中心频率可以在几千兆赫兹（GHz）的数量级。因此，在无线电频率处需要具有“基带”精度的滤波器来切出干扰源，这是比较困难的。公开了一种用于估计干扰源的相对强度和中心频率并将陷波滤波器的中心频率自适应地精确地置于干扰源位置的技术。

5. 发明授权

US08542708B1 Method and system for transporting constant bit rate clients across a packet interface 有权
标题翻译：用于在分组接口上传输恒定比特率客户端的方法和系统
公开(公告)号：US08542708B1
公开(公告)日：2013-09-24
申请号：US12795363
申请日：2010-06-07
申请人： Winston Ki-Cheong Mok , Karl Scheffer
发明人： Winston Ki-Cheong Mok , Karl Scheffer
IPC分类号： H04J3/06
CPC分类号： H04J3/0685 , H04J3/0658 , H04J3/0664 , H04J3/0697 , H04J3/1617
摘要： A method and apparatus are described for signaling the phase and frequency of constant bit rate (CBR) clients over a network or fabric. An incoming CBR client stream is segmented into variable sized segments, such as packets or general framing protocol (GFP) frames, and is regenerated on the other side of a fabric or network phase-locked to the incoming stream. Regeneration of the CBR client clock is based solely on segment sizes, and in the case of GFP frames, the rate of the SONET Path or OTN ODUk stream carrying the GFP frames. No overhead bytes are inserted into the GFP frames to convey phase and frequency information. The method disclosed is important for reducing the cost and complexity of communications networks by allowing CBR clients to be transported with low jitter and wander without requiring the source and sink network elements to be phase-locked to a common stratum reference.
摘要翻译：描述了一种用于通过网络或结构信令恒定比特率（CBR）客户端的相位和频率的方法和装置。传入的CBR客户端流被分段成可变大小的段，例如分组或通用帧协议（GFP）帧，并且在被锁定到输入流的结构或网络的另一侧上重新生成。 CBR客户端时钟的再生完全基于段大小，在GFP帧的情况下，是携带GFP帧的SONET路径或OTN ODUk流的速率。 GFP帧中没有插入开销字节来传送相位和频率信息。所公开的方法对于通过允许CBR客户端以低抖动和漂移传输而不需要将源和接收网络元件锁相到公共层参考来减少通信网络的成本和复杂性是重要的。

6. 发明授权

US07668210B1 Method and apparatus for reducing current demand variations in large fan-out trees 有权
标题翻译：用于减少大型扇出树的电流需求变化的方法和装置
公开(公告)号：US07668210B1
公开(公告)日：2010-02-23
申请号：US10830031
申请日：2004-04-23
申请人： Winston Ki-Cheong Mok , Scott A. Muma , Nicholas W. Rolheiser
发明人： Winston Ki-Cheong Mok , Scott A. Muma , Nicholas W. Rolheiser
IPC分类号： H04J3/04
CPC分类号： H04Q11/04 , H04J3/1611 , H04Q2213/13292 , H04Q2213/13339 , H04Q2213/13367
摘要： A method and apparatus are provided for reducing current demand variations in large fanout trees. The fanout tree is split into at least 2 sub-groups, each preferably with substantially equal parasitic capacitance. Data is then scrambled according to a scrambling sequence function to provide scrambled data having a constant number of bits that are toggled with respect to time, such as when observed in pairs of sub-groups. Functionally, an apparatus according to an embodiment of the present invention includes 3 blocks: a scrambler, egress logic, and a de-scrambler. The egress logic is simply a block of storage that can reorder the bytes received from the scrambler. The de-scrambler de-scrambles the retransmitted data based on the scrambling sequence function. Embodiments of the present invention can be applied to any system where data must fanout from a single source to many destinations, such as switches.
摘要翻译：提供了一种用于减少大型扇出树中的电流需求变化的方法和装置。扇出树被分成至少两个子组，每个子组优选地具有基本相等的寄生电容。然后根据加扰序列功能对数据进行加扰，以提供具有相对于时间被切换的固定位数的加扰数据，诸如当以子对对观察时。在功能上，根据本发明的实施例的装置包括3个块：加扰器，出口逻辑和解扰器。出口逻辑只是一个存储块，可以对从扰码器接收的字节进行重新排序。去扰频器基于加扰序列功能解密重传的数据。本发明的实施例可以应用于数据必须从单个源扇出到诸如交换机之类的许多目的地的任何系统。

7. 发明授权

US07656791B1 Systems and methods for hitless equipment protection 失效
标题翻译：无人机设备保护的系统和方法
公开(公告)号：US07656791B1
公开(公告)日：2010-02-02
申请号：US11780361
申请日：2007-07-19
申请人： Winston Ki-Cheong Mok , Pascal Routhier
发明人： Winston Ki-Cheong Mok , Pascal Routhier
IPC分类号： G01R31/08
CPC分类号： H04J3/14 , H04J3/0623 , H04J2203/006
摘要： Disclosed techniques include a method and apparatus that allow traffic to be switched between a working copy and a protected copy hitlessly. The control method simplifies implementation by advantageously distinguishing points within the apparatus wherein the working and protect streams should be virtually identical and aligned and points where the streams need only be identical but are tolerant of skew.
摘要翻译：公开的技术包括允许在工作副本和受保护的副本之间切换业务的方法和装置。控制方法通过有利地区分装置内的点来简化实现，其中工作和保护流应该实质上相同和对齐，并且指出流仅需要相同但容许偏斜的点。

8. 发明授权

US07417985B1 Egress selection switch architecture with power management 有权
标题翻译：出口选择开关架构与电源管理
公开(公告)号：US07417985B1
公开(公告)日：2008-08-26
申请号：US10765945
申请日：2004-01-29
申请人： Carl Dietz McCrosky , Andrew Milton Hughes , Winston Ki-Cheong Mok , Nick Rolheiser
发明人： Carl Dietz McCrosky , Andrew Milton Hughes , Winston Ki-Cheong Mok , Nick Rolheiser
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/3027 , H04L49/3072 , H04L49/40
摘要： A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.
摘要翻译：一种用于在时分多路复用存储器开关中降低功耗和数字逻辑噪声的方法和装置。该方法体现在出口选择交换（ESS）块体系结构中。如果给定组中的任何出口端口没有选择数据，则ESS块包括数据禁止块，其阻止数据传播，特别是入口颗粒到给定的出口端口组。入口数据禁用方法将端口分组，并通过端口组根除掉扇出树来节省电源，出口数据禁止方式基于端口组，通过从尾端禁用扇出树节省功耗应用入侵数据禁用方法。 ESS块还包括用于选择和存储给定入口颗粒以便最终输出到出口端口的颗粒选择块。

9. 发明授权

US08854963B1 Control and coordination of ODUflex bandwidth resizing operation 有权
标题翻译：控制和协调ODUflex带宽调整大小操作
公开(公告)号：US08854963B1
公开(公告)日：2014-10-07
申请号：US13466679
申请日：2012-05-08
申请人： Scott Muma , Winston Ki-Cheong Mok , Steven Scott Gorshe , Karl Scheffer
发明人： Scott Muma , Winston Ki-Cheong Mok , Steven Scott Gorshe , Karl Scheffer
IPC分类号： H04B10/27
CPC分类号： H04B10/27 , H04J3/1658 , H04J2203/0082 , H04J2203/0098 , H04L41/5025 , H04L43/0858 , H04L43/106 , H04L47/25 , H04L47/28
摘要： Methods and systems are provided for controlling elements in a signal path of a communication network to accommodate changes in the rate of a client signal. In particular, during the bandwidth resizing (BWR) portion of ITU-T Recommendation G.7044 Hitless Adjustment of ODUflex(GFP) protocol (HAO), the nodes in the chain along the ODUflex(GFP) signal path change their output rates in parallel such that FIFO over/underflow is avoided in the nodes. Certain embodiments provide mechanisms to synchronize and stabilize the nodes in a verifiable manner.
摘要翻译：提供了用于控制通信网络的信号路径中的元件以适应客户端信号速率变化的方法和系统。特别地，在ITU-T G.7044建议书（ODOflex（GFP）协议无效调整）（GFP）协议（HAO）的带宽调整大小（BWR）部分期间，沿着ODUflex（GFP）信号路径的链路中的节点将并行地改变其输出速率使得在节点中避免了FIFO溢出/下溢。某些实施例提供了以可验证的方式同步和稳定节点的机制。

10. 发明授权

US08413006B1 Error detection and correction in data and control words 有权
标题翻译：数据和控制字中的错误检测和纠正
公开(公告)号：US08413006B1
公开(公告)日：2013-04-02
申请号：US12705304
申请日：2010-02-12
申请人： Winston Ki-Cheong Mok , Steven Scott Gorshe , Matthew David Weber
发明人： Winston Ki-Cheong Mok , Steven Scott Gorshe , Matthew David Weber
IPC分类号： H03M13/00
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/1545 , H03M13/1575 , H04L5/0091
摘要： A method and system are provided to detect and correct errors in the Interlaken block code overhead bits. Specifically, a method is provided for determining the original transmitted information with a very high probability of correct interpretation. These approaches can also characterized by their minimal complexity. Further, such a method can operate on the received information in a manner that does not require consideration of special cases. Also, the method does not require the source to send any extra information or alter its current behavior in any way. Thus, the approaches described herein are compatible with all existing Interlaken sources and can provide immediate benefits.
摘要翻译：提供了一种方法和系统来检测和纠正Interlaken块码开销位中的错误。具体而言，提供了一种用于以正确解释的非常高概率来确定原始发送信息的方法。这些方法也可以以其最小的复杂性来表征。此外，这种方法可以不需要考虑特殊情况的方式对所接收的信息进行操作。此外，该方法不需要源发送任何额外的信息或以任何方式改变其当前行为。因此，本文所述的方法与所有现有的因特拉肯源兼容，并且可以提供直接的益处。

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