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    • 1. 发明授权
    • Hierarchical device spin-up control for serial attached devices
    • 串行连接设备的分层设备自升控制
    • US07474926B1
    • 2009-01-06
    • US11390264
    • 2006-03-28
    • Larrie Simon CarrHeng Liao
    • Larrie Simon CarrHeng Liao
    • G05B11/01
    • G06F1/266G11B19/209
    • A method and apparatus are provided for controlling the powering-up or spin-up of devices such as hard drives using expanders in a SAS topology. The method and apparatus provides a mechanism to coordinate spin-up control among a topology of expanders. The present invention enables an expander to both process the reception of the NOTIFY command to spin up attached devices and to propagate such command to further expanders. Hierarchical spin-up control provides an advantageous, in-band mechanism that controls the expanders within the topology to limit the total number of devices powering-up at any given time.
    • 提供了一种方法和装置,用于使用SAS拓扑中的扩展器来控制诸如硬盘驱动器等设备的上电或启动。 该方法和装置提供了一种协调扩展器拓扑结构中的自旋控制的机制。 本发明使得扩展器能够处理NOTIFY命令的接收以旋转附接的设备并且将这样的命令传播到另外的扩展器。 分层自旋控制提供了有利的带内机制,其控制拓扑内的扩展器以限制在任何给定时间上启动的设备的总数量。
    • 3. 发明授权
    • Serial attached SCSI broadcast primitive processor filtering for loop architectures
    • 串行连接SCSI广播原始处理器过滤循环架构
    • US08089902B1
    • 2012-01-03
    • US11326508
    • 2006-01-06
    • Heng LiaoKuan Hua TanLarrie Simon Carr
    • Heng LiaoKuan Hua TanLarrie Simon Carr
    • H04L12/28
    • H04L49/35H04L49/55
    • A method and system are provided for broadcast message filtering in SAS expanders. Common SAS topology defined by ANSI T10 specification only supports spanning tree topology (without loops) interconnection among multiple end devices and expander devices. Broadcast message filtering provides a mechanism to selectively discard broadcast messages, or primitives, in the SAS expanders to break the infinite loop path that broadcast primitives can traverse. This enables new SAS physical topologies with loops that are otherwise difficult or impossible to realize using SAS expanders that handle primitive broadcasts according to the definition of the SAS standard. By allowing redundant paths in a SAS topology, the problem of infinite broadcast flooding in SAS topology is reduced. Selectively forwarding broadcast messages can be based on whether the broadcast was originated at the source phy, or received by the source phy, or based on whether the source phy is a filtered phy.
    • 提供了一种方法和系统,用于SAS扩展器中的广播消息过滤。 ANSI T10规范定义的常规SAS拓扑仅支持多个终端设备和扩展器设备之间的生成树拓扑(无环路)互连。 广播消息过滤提供了选择性地丢弃SAS扩展器中的广播消息或原语以破坏广播原语可以遍历的无限循环路径的机制。 这使得新的SAS物理拓扑具有循环,否则难以或不可能根据SAS标准的定义处理原始广播的SAS扩展器来实现。 通过在SAS拓扑中允许冗余路径,减少了SAS拓扑中无限广播洪泛的问题。 选择性地转发广播消息可以基于广播是源自源phy还是由源phy接收,或者基于源phy是否是过滤的phy。
    • 9. 发明授权
    • State machine architecture with multiplexed random access memory
    • 具有复用随机存取存储器的状态机架构
    • US06333935B1
    • 2001-12-25
    • US09057509
    • 1998-04-09
    • Larrie Simon CarrWinston Ki-Cheong Mok
    • Larrie Simon CarrWinston Ki-Cheong Mok
    • H04B7212
    • G06F7/00H04J3/047
    • A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof. A null cycle generator coupled to the pipeline and to the controller inserts null cycles into the concurrently processed data streams at regular time intervals and outputs a NULL signal to the controller during each null cycle. A multiplexer coupled between the controller and the memory multiplexes access to the memory between the controller/pipeline, and an alternate controller. Read access to the memory by the controller or pipeline is inhibited while the NULL signal is output, and write access to the memory by the pipeline is inhibited while an OUTGOING NULL replica of the NULL signal is being output by the pipeline during the final clock cycle. Accordingly, the alternate controller may gain read access to the memory while the NULL signal is output, and may gain write access to the memory while the OUTGOING NULL signal is output.
    • 被并入包含多个数据字并由状态向量表征的单个数据流的多个时分复用数据流被同时处理。 状态向量存储在具有多个可寻址存储器位置的读写存储器中。 在初始时钟周期期间,流水线从数据流之一接收输入数据字,表征该数据流的输入状态向量和输入状态向量的存储器位置地址。 在一个或多个中间时钟周期期间,流水线处理输入数据字和输入状态向量以产生输出数据字和输出状态向量。 在最后的时钟周期期间,流水线将输出数据字传送到输出数据流,并将输出状态向量传送到上述存储位置地址。 耦合到存储器和管线的控制器同步其操作。 耦合到流水线和控制器的零周期发生器以固定的时间间隔将空周期插入到并行处理的数据流中,并且在每个空循环期间向控制器输出空信号。 耦合在控制器和存储器之间的复用器多路复用对控制器/流水线与备用控制器之间的存储器的访问。 当输出NULL信号时,控制器或流水线读取存储器的访问被禁止,并且在最终时钟周期期间管道输出NULL信号的OUTGOING NULL复制品时,流水线对存储器的写访问被禁止 。 因此,当输出NULL信号时,备用控制器可以获得对存储器的读取访问,并且可以在输出OUTGOING NULL信号时获得对存储器的写访问。