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1. 发明授权

US07417985B1 Egress selection switch architecture with power management 有权
标题翻译：出口选择开关架构与电源管理
公开(公告)号：US07417985B1
公开(公告)日：2008-08-26
申请号：US10765945
申请日：2004-01-29
申请人： Carl Dietz McCrosky , Andrew Milton Hughes , Winston Ki-Cheong Mok , Nick Rolheiser
发明人： Carl Dietz McCrosky , Andrew Milton Hughes , Winston Ki-Cheong Mok , Nick Rolheiser
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/3027 , H04L49/3072 , H04L49/40
摘要： A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.
摘要翻译：一种用于在时分多路复用存储器开关中降低功耗和数字逻辑噪声的方法和装置。该方法体现在出口选择交换（ESS）块体系结构中。如果给定组中的任何出口端口没有选择数据，则ESS块包括数据禁止块，其阻止数据传播，特别是入口颗粒到给定的出口端口组。入口数据禁用方法将端口分组，并通过端口组根除掉扇出树来节省电源，出口数据禁止方式基于端口组，通过从尾端禁用扇出树节省功耗应用入侵数据禁用方法。 ESS块还包括用于选择和存储给定入口颗粒以便最终输出到出口端口的颗粒选择块。

2. 发明授权

US08085764B1 Egress selection switch architecture with power management 有权
标题翻译：出口选择开关架构与电源管理
公开(公告)号：US08085764B1
公开(公告)日：2011-12-27
申请号：US12175243
申请日：2008-07-17
申请人： Carl Dietz McCrosky , Andrew Milton Hughes , Winston Ki-Cheong Mok , Nicholas Wayne Rolheiser
发明人： Carl Dietz McCrosky , Andrew Milton Hughes , Winston Ki-Cheong Mok , Nicholas Wayne Rolheiser
IPC分类号： H04L12/50
CPC分类号： H04L49/3027 , H04L49/3072 , H04L49/40
摘要： A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.
摘要翻译：一种用于在时分多路复用存储器开关中降低功耗和数字逻辑噪声的方法和装置。该方法体现在出口选择交换（ESS）块体系结构中。如果给定组中的任何出口端口没有选择数据，则ESS块包括数据禁止块，其阻止数据传播，特别是入口颗粒到给定的出口端口组。入口数据禁用方法将端口分组，并通过端口组根除掉扇出树来节省电源，出口数据禁止方式基于端口组，通过从尾端禁用扇出树节省功耗应用入侵数据禁用方法。 ESS块还包括用于选择和存储给定入口颗粒以便最终输出到出口端口的颗粒选择块。

3. 发明授权

US06876650B2 Bipartite graphical connecting scheduling in time and space switch fabrics 失效
标题翻译：时间和空间交换结构中的双向图形连接调度
公开(公告)号：US06876650B2
公开(公告)日：2005-04-05
申请号：US09766602
申请日：2001-01-23
申请人： Carl Dietz McCrosky , Andrew Milton Hughes , Kenneth Evert Sailor , Paul Edmund Somogyi , James Ames Meacham, II
发明人： Carl Dietz McCrosky , Andrew Milton Hughes , Kenneth Evert Sailor , Paul Edmund Somogyi , James Ames Meacham, II
IPC分类号： H04Q11/06 , H04L12/50 , H04Q11/50
CPC分类号： H04Q11/06 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13056 , H04Q2213/13166 , H04Q2213/13292 , H04Q2213/1334
摘要： A method of adding a new connection (c, d) to a time:space:time switch fabric. The fabric has a set I of k input elements, a set M of m switch elements, and a set O of l output elements. Each input element contributes one input to each switch element, and each output element receives one output from each switch element. A state Sm characterizes the switch elements as a set of ordered pairs (i, j), where (i, j) ε Sm if and only if the jth output element is coupled to the ith input element through one of the switch elements. The range of Sm is the set of outputs of Sm such that if j ε range(Sm) then (i, j) ε Sm for some i ε I. The domain of Sm is the set of inputs of Sm such that if i ε domain(Sm) then (i, j) ε Sm for some j ε O.
摘要翻译：一种将新连接（c，d）添加到time：time：time switch fabric的方法。织物具有k个输入元件的集合I，m个开关元件的集合M和l个输出元素的集合O。每个输入元件为每个开关元件提供一个输入，并且每个输出元件从每个开关元件接收一个输出。状态Sm将开关元件表征为一组有序对（i，j），其中（i，j）epsilon Sm，当且仅当第j个输出元件通过一个第i个输入元件耦合到第i个输入元件的开关元件。 Sm的范围是Sm的输出集合，使得对于一些i∈I，如果jε范围（Sm）则是（i，j）εSm。Sm的域是Sm的输入集合，使得如果iε （Sm），然后（i，j）为某些jεO的εSm。

4. 发明授权

US06870831B2 Flexible, self-aligning time and space switch fabrics 失效
标题翻译：灵活，自动对准的时间和空间交换结构
公开(公告)号：US06870831B2
公开(公告)日：2005-03-22
申请号：US09845171
申请日：2001-05-01
申请人： Andrew Milton Hughes , Douglas Konkin , Carl Dietz McCrosky , Winston Mok , Jeffrey Scott Roe , Kenneth Evert Sailor
发明人： Andrew Milton Hughes , Douglas Konkin , Carl Dietz McCrosky , Winston Mok , Jeffrey Scott Roe , Kenneth Evert Sailor
IPC分类号： H04Q11/06 , H04L12/50
CPC分类号： H04Q11/06 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/13322 , H04Q2213/1334 , H04Q2213/13341 , H04Q2213/1336 , H04Q2213/13367
摘要： A time:space:time switch fabric incorporating an odd integer number of spatially distributed data switches and a plurality of spatially distributed data serializers. Each data switch has a first plurality of ingress ports, an equal plurality of egress ports, and a space switch for selectably interconnecting any one of the ingress ports to any one of the egress ports. Each data serializer has an input bus for receiving signals to be routed through the switch fabric, an output bus for outputting signals routed through the switch fabric, a plurality of egress ports selectably connectible to any one of the data switch ingress ports, and an equal plurality of ingress ports selectably connectible to any one of the data switch egress ports. The ingress/egress ports are characterized by: (A) p planes, where p is a power-of-two integer less than or equal to the number of data serializer ingress and egress ports; (B) s stages, where s is an odd integer number; and, (C) a depth d, where d is a power-of-two integer less than or equal to the number of data switch ingress and egress ports.
摘要翻译：时间：空间：结合有奇数整数个空间分布数据交换机的时间交换结构和多个空间分布的数据串行器。每个数据交换机具有第一多个入口端口，相等的多个出口端口和用于将任何一个入口端口可选地互连到任何一个出口端口的空间交换机。每个数据串行器具有用于接收要通过交换结构路由的信号的输入总线，用于输出通过交换结构路由的信号的输出总线，可选地可连接到任何一个数据交换机入口端口的多个出口端口，以及相等的多个入口端口可选择地连接到数据交换机出口端口中的任何一个。入口/出口端口的特征在于：（A）p平面，其中p是小于或等于数据串行器入口和出口端口数量的二进制整数;（B）s级，其中s是奇整数; 和（C）深度d，其中d是小于或等于数据交换机入口和出口端口数量的二进制整数。

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