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1. 发明授权

US07250669B2 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US07250669B2
公开(公告)日：2007-07-31
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
IPC分类号： H01L29/00
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

2. 发明授权

US06869884B2 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US06869884B2
公开(公告)日：2005-03-22
申请号：US10225828
申请日：2002-08-22
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

3. 发明授权

US06716693B1 Method of forming a surface coating layer within an opening within a body by atomic layer deposition 有权
标题翻译：通过原子层沉积在体内的开口内形成表面涂层的方法
公开(公告)号：US06716693B1
公开(公告)日：2004-04-06
申请号：US10400511
申请日：2003-03-27
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218234
CPC分类号： H01L28/10 , H01F17/0033 , H01F41/042 , H01L21/76838 , H01L23/522 , H01L23/5227 , H01L23/53238 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An improved new process for fabricating multilevel interconnected vertical channels and horizontal channels or tunnels. The method has broad applications in semiconductors, for copper interconnects and inductors, as well as, in the field of bio-sensors for mini- or micro-columns in gas or liquid separation, gas/liquid chromatography, and in capillary separation techniques. In addition, special techniques are described to deposit by atomic layer deposition, ALD, a copper barrier layer and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a type of damascene process, to form copper interconnects and inductors.
摘要翻译：一种用于制造多层互连垂直通道和水平通道或隧道的改进的新工艺。该方法在半导体，铜互连和电感器以及在气体或液体分离中的微型或微型柱的生物传感器领域，气/液相色谱和毛细管分离技术领域具有广泛的应用。此外，描述了通过原子层沉积，ALD，铜阻挡层和用于化学镀铜的种子层，一种镶嵌工艺中的填充沟槽和沟道或隧道开口来沉积特殊技术以形成铜互连和电感器。

4. 发明授权

US06903013B2 Method to fill a trench and tunnel by using ALD seed layer and electroless plating 有权
标题翻译：通过使用ALD种子层和化学镀填充沟槽和隧道的方法
公开(公告)号：US06903013B2
公开(公告)日：2005-06-07
申请号：US10439923
申请日：2003-05-16
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yong Ju , Jia Zhen Zheng
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yong Ju , Jia Zhen Zheng
IPC分类号： H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/28562 , H01L21/76843 , H01L21/76873 , H01L23/5227 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.
摘要翻译：已经开发了一种改进的方法，通过原子层沉积，ALD，用于化学镀铜的铜屏障和种子层，在镶嵌工艺中的填充沟槽和沟道或隧道开口，用于制造互连和电感器。概述本发明方法的工艺流程如下：（1）形成沟槽和通道，（2）铜屏障和晶种的原子层沉积，（3）铜的无电沉积，（4）化学机械抛光的过量铜，和（5）阻挡层沉积，SiN，形成铜互连和电感器。

5. 发明授权

US06852605B2 Method of forming an inductor with continuous metal deposition 有权
公开(公告)号：US06852605B2
公开(公告)日：2005-02-08
申请号：US10427287
申请日：2003-05-01
申请人： Chit Hwei Ng , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
发明人： Chit Hwei Ng , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
IPC分类号： H01F17/00 , H01L21/02 , H01L23/522 , H01L21/20
CPC分类号： H01L28/10 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

6. 发明申请

US20050009357A1 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US20050009357A1
公开(公告)日：2005-01-13
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
发明人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

7. 发明授权

US07049201B2 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US07049201B2
公开(公告)日：2006-05-23
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
发明人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

8. 发明授权

US06924202B2 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact 有权
标题翻译：具有自对准发射极和侧壁基极接触的异质结双极晶体管
公开(公告)号：US06924202B2
公开(公告)日：2005-08-02
申请号：US10683142
申请日：2003-10-09
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。在基底沟槽中形成具有侧壁部分和底部的本征基底结构。在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。在基极接触层和发射极结构之上形成层间电介质层。通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

9. 发明授权

US06908824B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US06908824B2
公开(公告)日：2005-06-21
申请号：US10703284
申请日：2003-11-06
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

10. 发明授权

US06881976B1 Heterojunction BiCMOS semiconductor 失效
标题翻译：异质结BiCMOS半导体
公开(公告)号：US06881976B1
公开(公告)日：2005-04-19
申请号：US10705163
申请日：2003-11-06
申请人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
发明人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/04 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.
摘要翻译：因此，提供BiCMOS半导体及其制造方法。提供具有集电极区域的半导体衬底。在集电极区域上形成伪栅极。在伪栅极中形成发射器窗口以形成外部基极结构。在伪栅极的一部分下面的底切区域形成为在底切区域中提供内部基极结构。发射极结构在内部基极结构的发射极窗口中形成。在半导体衬底上形成层间电介质层，并且通过层间电介质层到集电极区域，非本征基极结构和发射极结构形成连接。本征基础结构包括诸如硅和硅 - 锗的复合半导体材料或硅 - 锗 - 碳或其组合。

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