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1. 发明申请

US20060044895A1 System and method for capacitive coupled via structures in information handling system circuit boards 有权
标题翻译：用于信息处理系统电路板中电容耦合通孔结构的系统和方法
公开(公告)号：US20060044895A1
公开(公告)日：2006-03-02
申请号：US10924629
申请日：2004-08-24
申请人： Abeye Teshome , Lan Zhang
发明人： Abeye Teshome , Lan Zhang
IPC分类号： G11C29/00
CPC分类号： H05K1/0216 , H05K1/0263 , H05K1/112 , H05K1/162 , H05K2201/0792 , H05K2201/09309 , H05K2201/10734 , Y10T29/49128 , Y10T29/49169
摘要： Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.
摘要翻译：通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔被对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速解耦有关的寄生电感的影响。期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。

2. 发明申请

US20080277153A1 System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards 审中-公开
标题翻译：信息处理系统电路板中电容耦合VIA结构的系统与方法
公开(公告)号：US20080277153A1
公开(公告)日：2008-11-13
申请号：US11931698
申请日：2007-10-31
申请人： Abeye Teshome , Lan Zhang
发明人： Abeye Teshome , Lan Zhang
IPC分类号： H01R12/06
CPC分类号： H05K1/0216 , H05K1/0263 , H05K1/112 , H05K1/162 , H05K2201/0792 , H05K2201/09309 , H05K2201/10734 , Y10T29/49128 , Y10T29/49169
摘要： Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.
摘要翻译：通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔被对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速解耦有关的寄生电感的影响。期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。

3. 发明授权

US07305760B2 System and method for capacitive coupled via structures in information handling system circuit boards 有权
标题翻译：用于信息处理系统电路板中电容耦合通孔结构的系统和方法
公开(公告)号：US07305760B2
公开(公告)日：2007-12-11
申请号：US10924629
申请日：2004-08-24
申请人： Abeye Teshome , Lan Zhang
发明人： Abeye Teshome , Lan Zhang
IPC分类号： H01R43/00 , H05K13/00
CPC分类号： H05K1/0216 , H05K1/0263 , H05K1/112 , H05K1/162 , H05K2201/0792 , H05K2201/09309 , H05K2201/10734 , Y10T29/49128 , Y10T29/49169
摘要： Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.
摘要翻译：通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速去耦合有关的寄生电感的影响。期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。

4. 发明授权

US06801880B2 System and method for minimizing a loading effect of a via by tuning a cutout ratio 有权
标题翻译：通过调整切割比来最小化通孔的负载效应的系统和方法
公开(公告)号：US06801880B2
公开(公告)日：2004-10-05
申请号：US10187927
申请日：2002-07-02
申请人： Lan Zhang , Abeye Teshome
发明人： Lan Zhang , Abeye Teshome
IPC分类号： G06F1750
CPC分类号： H05K1/0216 , H05K1/116 , H05K3/429 , H05K2201/09718 , H05K2201/09781 , H05K2203/171 , Y10T29/49004
摘要： An information handling system that includes a circuit board for mounting and coupling components of the information handling system. The circuit board includes a trace, a via coupled to the trace, and a cutout region surrounding the via and having a first diameter selected to minimize a loading effect of a via on a signal conveyed on the trace.
摘要翻译：一种信息处理系统，包括用于安装和耦合信息处理系统的组件的电路板。电路板包括迹线，耦合到迹线的通孔和围绕通孔的切除区域，并且具有选择的最小直径，以最小化通孔对在迹线上传送的信号的负载效应。

5. 发明申请

US20120131666A1 Virtual Appliance Pre-Boot Authentication 有权
标题翻译：虚拟设备预引导认证
公开(公告)号：US20120131666A1
公开(公告)日：2012-05-24
申请号：US13361589
申请日：2012-01-30
申请人： Yuan-Chang Lo , Aaron Merkin , Abeye Teshome
发明人： Yuan-Chang Lo , Aaron Merkin , Abeye Teshome
IPC分类号： G06F21/00
CPC分类号： G06F21/31 , G06F21/575 , H04L9/3231
摘要： A system for pre-boot authentication of a virtual appliance includes one or more subsystems to receive a command to power-on an information handling system (IHS). After receiving the command to power-on the IHS, the system initializes a power-on self test (POST), passes control of the IHS to a hypervisor, loads a concurrent service environment (CSE), requests user credentials, receives user credentials, authenticates user credentials using the CSE and authorizes a specific operating system image from a plurality of images to run on the IHS via the virtual appliance after the user credentials are authenticated.
摘要翻译：用于虚拟设备的预引导认证的系统包括一个或多个子系统，用于接收用于对信息处理系统（IHS）通电的命令。系统收到IHS上电命令后，初始化开机自检（POST），将IHS的控制传递给管理程序，加载并发服务环境（CSE），请求用户凭据，接收用户凭据，使用CSE认证用户凭证，并授权来自多个图像的特定操作系统映像在认证用户凭据之后通过虚拟设备在IHS上运行。

6. 发明申请

US20070244684A1 Method to model 3-D PCB PTH via 审中-公开
标题翻译： 3-D PCB PTH通道的建模方法
公开(公告)号：US20070244684A1
公开(公告)日：2007-10-18
申请号：US11405242
申请日：2006-04-17
申请人： Rajen Murugan , Jimmy Pike , Abeye Teshome
发明人： Rajen Murugan , Jimmy Pike , Abeye Teshome
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/0216 , H05K1/0237 , H05K3/0005 , H05K3/429 , H05K2201/09327
摘要： A methodology may be used that takes into account the inductive coupling of current transients on the power rails of a printed circuit board (PCB) that may be coupled to the barrel of a via. By taking into account the coupling of the current transients on the power rails of the PCB, more accurate and realistic modeling results may be obtained. Inductive coupling of the current transients from the power rails may be more pronounced at higher frequencies and may be additive for more layer transitions (e.g., more via transitions) of the PCB.
摘要翻译：可以使用考虑到可以耦合到通孔的筒的印刷电路板（PCB）的电源轨上的电流瞬变的电感耦合的方法。通过考虑PCB上电源线上的电流瞬变的耦合，可以获得更精确和逼真的建模结果。来自电源轨的电流瞬变的感性耦合可能在较高频率下更为显着，并且可能对于PCB的更多层转变（例如更多的经由转变）而言是相加的。

7. 发明申请

US20130268939A1 SYSTEMS AND METHODS FOR TASK EXECUTION ON A MANAGED NODE 有权
标题翻译：管理节点执行任务的系统和方法
公开(公告)号：US20130268939A1
公开(公告)日：2013-10-10
申请号：US13911272
申请日：2013-06-06
申请人： Abeye Teshome , Aaron Merkin
发明人： Abeye Teshome , Aaron Merkin
IPC分类号： G06F9/44
CPC分类号： G06F9/44 , G06F9/5094 , G06F2209/501 , Y02D10/22
摘要： Systems and methods for executing tasks on a managed node remotely coupled to a management node are provided. A management controller of the management node may be configured to determine at least one execution policy for a task, schedule the task for execution, receive system information data from the managed node, based at least on the received system information, determine if the received system information complies with the at least one execution policy, and if the received information complies with the at least one execution policy, forward the task from the management controller to the managed node for execution.
摘要翻译：提供了用于在远程耦合到管理节点的受管节点上执行任务的系统和方法。管理节点的管理控制器可以被配置为至少基于所接收的系统信息来确定用于任务的至少一个执行策略，调度执行任务，从被管理节点接收系统信息数据，确定所接收的系统信息符合至少一个执行策略，并且如果接收到的信息符合至少一个执行策略，则将该任务从管理控制器转发到被管理节点以供执行。

8. 发明授权

US08484652B2 Systems and methods for task execution on a managed node 有权
标题翻译：受管节点上任务执行的系统和方法
公开(公告)号：US08484652B2
公开(公告)日：2013-07-09
申请号：US12533117
申请日：2009-07-31
申请人： Abeye Teshome , Aaron Merkin
发明人： Abeye Teshome , Aaron Merkin
IPC分类号： G06F9/46 , G06F9/44 , G06F9/455 , G06F1/00 , G06F1/32
CPC分类号： G06F9/44 , G06F9/5094 , G06F2209/501 , Y02D10/22
摘要： Systems and methods for executing tasks on a managed node remotely coupled to a management node are provided. A management controller of the management node may be configured to determine at least one execution policy for a task, schedule the task for execution, receive system information data from the managed node, based at least on the received system information, determine if the received system information complies with the at least one execution policy, and if the received information complies with the at least one execution policy, forward the task from the management controller to the managed node for execution.
摘要翻译：提供了用于在远程耦合到管理节点的受管节点上执行任务的系统和方法。管理节点的管理控制器可以被配置为至少基于所接收的系统信息来确定用于任务的至少一个执行策略，调度执行任务，从被管理节点接收系统信息数据，确定所接收的系统信息符合至少一个执行策略，并且如果接收到的信息符合至少一个执行策略，则将该任务从管理控制器转发到被管理节点以供执行。

9. 发明授权

US06219255B1 Method and apparatus for reducing EMI in a computer system 有权
标题翻译：用于在计算机系统中降低EMI的方法和装置
公开(公告)号：US06219255B1
公开(公告)日：2001-04-17
申请号：US09137472
申请日：1998-08-20
申请人： Abeye Teshome
发明人： Abeye Teshome
IPC分类号： H05K111
CPC分类号： H05K1/0253 , H05K1/0216 , H05K1/0262 , H05K9/0039 , H05K2201/09245 , H05K2201/093 , H05K2201/09345 , H05K2201/09663 , H05K2201/09781 , H05K2201/10689 , Y10T29/49155
摘要： A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer. The interconnect is further disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region. A method for reducing a source of EMI in a multilayer printed circuit board is also disclosed.
摘要翻译：计算机系统包括微处理器，耦合以向微处理器提供信号输入的输入，耦合到微处理器的大容量存储器，用于将微处理器耦合到显示器的视频控制器，耦合以提供存储以便于执行计算机程序的存储器以及用于在其上安装微处理器的多层印刷电路板。多层印刷电路板提供降低的电磁干扰（EMI）并且包括至少两层。所述多层印刷电路板还包括第一层上的第一导电段，所述第一层上的第二导电区段，所述第二区段通过初级间隙与所述第一区段分离，以及在第二层上的导电互连，所述互连用于在其中携带高频信号。第二层从第一层横向设置并基本平行于第一层。所述互连被进一步布置成用于在交叉区域中跨越所述第一段到所述第二段，并且其中所述第一段和所述第二段的进一步特征在于所述交叉区域中的次级间隙，所述次级间隙小于用于在交叉区域中提供增加的耦合的主要间隙。还公开了一种用于减少多层印刷电路板中的EMI源的方法。

10. 发明授权

US5974497A Computer with cache-line buffers for storing prefetched data for a misaligned memory access 失效
标题翻译：具有缓存线缓冲区的计算机，用于存储未对齐内存访问的预取数据
公开(公告)号：US5974497A
公开(公告)日：1999-10-26
申请号：US861778
申请日：1997-05-22
申请人： Abeye Teshome
发明人： Abeye Teshome
IPC分类号： G06F12/08 , G06F13/40 , G06F13/00
CPC分类号： G06F12/0835 , G06F12/0886 , G06F13/4059
摘要： In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses from the peripheral device is disclosed. The buffer is included in a bridge device for interfacing the two computer buses and controlling when the peripheral device may access the main memory. When the peripheral device attempts to read data from the main memory that is duplicated in the cache and that has become stale, the bridge device initiates a write back operation to update specific data portions of the main memory corresponding to the read request. The bridge device uses look-ahead techniques such as bursting or pipelining to streamline the data coming from the cache to the main memory and to the peripheral device. When the peripheral device requests a misaligned memory read operation, upon termination of the read access due to preemption of the peripheral device, the cache line containing the remainder of the requested data is written back to the main memory, and stored in the buffler. The bridge device can then use the data stored in the buffer to respond to subsequent memory access requests from the peripheral device.
摘要翻译：在包括两个总线的计算机中，主存储器，写回高速缓冲存储器和外围设备，公开了一种用于提供总线间缓冲器以支持来自外围设备的连续主存储器访问的方法和装置。缓冲器包括在用于连接两台计算机总线的桥接设备中，并且控制外围设备何时可以访问主存储器。当外围设备尝试从主存储器中读取数据，该数据被复制在高速缓存中并且已经变得过时时，桥接器件启动回写操作以更新与读取请求对应的主存储器的特定数据部分。桥接器件使用诸如突发或流水线之类的先行技术将来自高速缓存的数据简化为主存储器和外围设备。当外围设备请求不对齐的存储器读取操作时，由于外围设备的抢占而导致读取访问终止，包含所请求数据的其余部分的高速缓存行被写回到主存储器中，并存储在缓冲器中。然后，桥接器件可以使用存储在缓冲器中的数据来响应来自外围设备的后续存储器访问请求。

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