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    • 4. 发明授权
      US4195352A Split programmable logic array 失效
    • Split programmable logic array
    • 分割可编程逻辑阵列
    • US4195352A
    • 1980-03-25
    • US814054
    • 1977-07-08
    • George K. Tu , George E. Mager , Lamar T. Baker , Robert E. Markle
    • George K. Tu , George E. Mager , Lamar T. Baker , Robert E. Markle
    • H03K19/177 , G06F9/00 , H03K19/08 , H03K19/34
    • H03K19/17716
    • A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.TABLE OF CONTENTSSubjectBackground of the InventionSummary of the InventionBrief Description of the DrawingsDetailed Description of the Preferred EmbodimentThe System Block DiagramMicroprocessor Unit Pin DesignationsClock and Timing SignalsSystem TimingThe ROMThe Stack AreaThe RAM AreaElimination of Race Conditions in the RAMThe ALU and ControlTime Slot End PredictorThe CROMBit Manipulation SchemeData Pad Input/OutputPrecharged Data Line DriverBus ControlTest CircuitrySplit PLA ControlThe S-CounterDetails of Logic BlocksThe MOS/LSI ChipThe Chip Test FunctionsThe Instruction Set
    • 面罩可编程逻辑阵列（PLA），用于产生给定一定数字输入的特定数字输出。 到PLA的输入信号首先通过一系列AND门，产生预定数量的产品项。 然后，产品信号通过一组或门以成为最终的输出信号。 在本发明中，AND门和OR门通过使用NOR-NOR逻辑来实现。 第一组NOR门在阵列中实现以接收输入信号并产生产品术语。 第二组和第三组NOR门形成两个阵列。 然后，这两个阵列位于第一阵列的任一侧，以接收选定的产品信号，以产生最终的输出信号。 实际上，PLA的OR部分已经分成两个阵列。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US4156291A Circuitry for eliminating double ram row addressing 失效
    • Circuitry for eliminating double ram row addressing
    • 消除双排行寻址的电路
    • US4156291A
    • 1979-05-22
    • US814237
    • 1977-07-08
    • Lamar T. Baker
    • Lamar T. Baker
    • G11C11/418 , G11C7/00 , G11C8/00
    • G11C11/418
    • Word select circuitry which eliminates double RAM row addressing is used with a read-write memory system of the type employing a plurality of word select lines. Sample and latch devices store input memory address data sampled at a predetermined rate. The devices provide at their outputs the stored data and its complement until new input memory address data is sampled. Additional circuitry is provided for producing a sampling signal which causes the latch devices to sample the input memory address data at the predetermined rate. A decoder provides signals to activate a selected one of the word select lines in response to the data signals received from the outputs of the latch devices. Additional circuitry is coupled to the decoder to produce a signal which precludes the activation of all of the word select lines when the latch devices are sampling input memory address data. In the preferred embodiment, all of the aforementioned circuitry is contained on a single semiconductor chip. In addition, a timing device on the chip is provided for synchronizing the data flow in the memory system.
    • 消除双RAM行寻址的字选择电路与采用多个字选择线的类型的读写存储器系统一起使用。 采样和锁存装置存储以预定速率采样的输入存储器地址数据。 这些设备在其输出端提供存储的数据及其补码，直到新的输入存储器地址数据被采样为止。 提供附加电路用于产生采样信号，其使得锁存器件以预定速率对输入存储器地址数据进行采样。 响应于从锁存装置的输出接收的数据信号，解码器提供信号以激活所选择的一个字选择线。 附加电路耦合到解码器以产生当锁存器件正在对输入存储器地址数据进行采样时，排除所有字选择线的激活的信号。 在优选实施例中，所有上述电路都包含在单个半导体芯片上。 此外，芯片上的定时装置被提供用于使存储器系统中的数据流同步。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US4144589A Precharged data line driver 失效
    • Precharged data line driver
    • 预充电数据线驱动
    • US4144589A
    • 1979-03-13
    • US813999
    • 1977-07-08
    • Lamar T. Baker , George K. Tu
    • Lamar T. Baker , George K. Tu
    • G11C11/4094 , G11C11/419 , G11C11/40
    • G11C11/419 , G11C11/4094
    • For use in a microprocessor on a single semiconductor chip, circuitry responsive to a timing signal and a data signal for discharging a precharged data line to correspond to the data to be transmitted on the data line. First and second enhancement-type field effect devices are connected in series with the drain of the first device being connected to the data line and the source of the second device being connected to a source voltage. The gate of one of the field effect devices provides an input for the timing signal. The gate of the remaining field effect device provides an input for the data signal. A depletion-type field effect device has its source and gate coupled to the series connection point and its drain connected to a drain voltage source. The depletion-type field effect device prevents a charge redistribution from the data line to the series field effect devices when these devices are not discharging the line.
    • 用于在单个半导体芯片上的微处理器中，响应于定时信号的电路和用于对预先充电的数据线进行放电的数据信号以对应于要在数据线上发送的数据。 第一和第二增强型场效应器件与第一器件的漏极串联连接到数据线，并且第二器件的源极连接到源极电压。 场效应装置之一的门为定时信号提供输入。 剩余场效应器件的栅极为数据信号提供输入。 耗尽型场效应器件的源极和栅极耦合到串联连接点，其漏极连接到漏极电压源。 耗尽型场效应器件当这些器件不放电时，防止从数据线到串联场效应器件的电荷再分配。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US4144561A Chip topography for MOS integrated circuitry microprocessor chip 失效
    • Chip topography for MOS integrated circuitry microprocessor chip
    • US4144561A
    • 1979-03-13
    • US813902
    • 1977-07-08
    • George K. Tu , Lamar T. Baker , Robert E. Markle , George E. Mager
    • George K. Tu , Lamar T. Baker , Robert E. Markle , George E. Mager
    • G06F15/78 , H01L27/02 , G06F1/00 , G06F9/00
    • H01L27/0207
    • The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM. A bus control area is located in the upper right hand corner of the chip. A programmed control area is located between the ALU area and the bus control area in the upper right hand portion of the chip and is coupled to the data bus for receiving instruction words from the program storage area and for generating commands which define the operation of the microprocessor in response to the instruction words. A clock/T-counter is located in the lower right hand corner and is used for synchronizing data signal flow in the micrprocessor. A stack area is located in the lower right hand portion of the chip. Within this stack area are various registers located from top to bottom as follows; write X circuitry, an X register a stack array, stack read/write circuitry, a memory address register, and an incrementer. A stack control is located between the aforementioned stack circuitry and the right hand edge. In addition, a RAM decode is located between the RAM and the left hand edge, a ROM column decode is located between the ROM and the bottom edge, and a ROM row decode is located between the ROM and the stack area.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US4196357A Time slot end predictor 失效
    • Time slot end predictor
    • 时隙结束预测器
    • US4196357A
    • 1980-04-01
    • US814064
    • 1977-07-08
    • Lamar T. Baker
    • Lamar T. Baker
    • G06F1/10 , H03K13/34 , H03K5/15 , H03K17/16 , H03K19/08
    • G06F1/10
    • For use in a microprocessor on a single semiconductor chip, a circuit responsive to first and second non-overlapping time signals for removing timed delay in a first data line. A first enhancement-type field effect device has its drain coupled to the first data line and its gate providing an input for the first timing signal. A second enhancement-type field effect device has its drain coupled to the source of the first device and its source coupled to a source voltage. The source voltage is at ground potential. A third enhancement field effect device has its drain coupled to the first data line, its source coupled to the gate of the second device, and its gate providing an input for the second timing signal.
    • 为了在单个半导体芯片上的微处理器中使用响应于第一和第二非重叠时间信号的电路，用于消除第一数据线中的定时延迟。 第一增强型场效应器件的漏极耦合到第一数据线，其栅极提供用于第一定时信号的输入。 第二增强型场效应器件的漏极耦合到第一器件的源极，其源极耦合到源极电压。 源电压处于地电位。 第三增强场效应器件的漏极耦合到第一数据线，其源极耦合到第二器件的栅极，并且其栅极为第二定时信号提供输入。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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