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    • 5. 发明授权
    • Integrated device having MOS transistors which enable positive and
negative voltage swings
    • 具有MOS晶体管的集成器件,其实现正负电压摆幅
    • US5321293A
    • 1994-06-14
    • US88945
    • 1993-07-12
    • Mohamad M. MojaradiTuan VoJaime LermaSteven A. Buhler
    • Mohamad M. MojaradiTuan VoJaime LermaSteven A. Buhler
    • H01L29/78H01L27/02H01L27/092H03K17/30H03K3/01
    • H01L27/0925H01L27/0251H03K17/302
    • A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit. Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage. Utilizing this feature of a MOS transistor provides a way to design an integrated circuit which can handle negative voltage swings as well as positive voltage swings.
    • 公开了一种与用于接收TTL输入电压并且相对于p型或n型衬底产生大的负和正电压摆幅的CMOS电路集成的半导体电路。 本发明基于消除作为任何集成电路的要求的静电放电(ESD)保护电路。 消除ESD保护电路也消除了ESD保护电路的钳位特性,因此电路可以被驱动到PMOS电路的负电压和NMOS电路的正电压。 这提供了将制造在n阱内的p型衬底上的P沟道型金属氧化物硅场效应(PMOS)晶体管的漏极连接到低于衬底电压的电压的可能性。 此外,在P阱内的n型衬底上制造的n沟道型金属氧化物硅场效应(NMOS)晶体管中,漏极可以连接到高于衬底电压的电压。 利用MOS晶体管的这一特征提供了一种设计可以处理负电压摆幅以及正电压摆幅的集成电路的方法。