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1. 发明授权

US4195352A Split programmable logic array 失效
标题翻译：分割可编程逻辑阵列
公开(公告)号：US4195352A
公开(公告)日：1980-03-25
申请号：US814054
申请日：1977-07-08
申请人： George K. Tu , George E. Mager , Lamar T. Baker , Robert E. Markle
发明人： George K. Tu , George E. Mager , Lamar T. Baker , Robert E. Markle
IPC分类号： H03K19/177 , G06F9/00 , H03K19/08 , H03K19/34
CPC分类号： H03K19/17716
摘要： A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.TABLE OF CONTENTSSubjectBackground of the InventionSummary of the InventionBrief Description of the DrawingsDetailed Description of the Preferred EmbodimentThe System Block DiagramMicroprocessor Unit Pin DesignationsClock and Timing SignalsSystem TimingThe ROMThe Stack AreaThe RAM AreaElimination of Race Conditions in the RAMThe ALU and ControlTime Slot End PredictorThe CROMBit Manipulation SchemeData Pad Input/OutputPrecharged Data Line DriverBus ControlTest CircuitrySplit PLA ControlThe S-CounterDetails of Logic BlocksThe MOS/LSI ChipThe Chip Test FunctionsThe Instruction Set
摘要翻译：面罩可编程逻辑阵列（PLA），用于产生给定一定数字输入的特定数字输出。到PLA的输入信号首先通过一系列AND门，产生预定数量的产品项。然后，产品信号通过一组或门以成为最终的输出信号。在本发明中，AND门和OR门通过使用NOR-NOR逻辑来实现。第一组NOR门在阵列中实现以接收输入信号并产生产品术语。第二组和第三组NOR门形成两个阵列。然后，这两个阵列位于第一阵列的任一侧，以接收选定的产品信号，以产生最终的输出信号。实际上，PLA的OR部分已经分成两个阵列。

2. 发明授权

US4194241A Bit manipulation circuitry in a microprocessor 失效
标题翻译：微处理器中的位操作电路
公开(公告)号：US4194241A
公开(公告)日：1980-03-18
申请号：US814051
申请日：1977-07-08
申请人： George E. Mager
发明人： George E. Mager
IPC分类号： G06F9/308 , G06F7/00 , G06F9/08
CPC分类号： G06F9/30018
摘要： A method and apparatus for bit manipulation in a digital processor being suitable for executing a plurality of instructions stored in a memory and carried from said memory in accordance with a plurality of machine cycles, each of said instructions including an operational code. A decoder generates a bit mask in response to an operational code. The bit mask generated is in binary digits which are the complement of 2.sup.i where i is the number in base 10 represented by the three least significant bits of the operational code. A register stores the particular bit-mask. An additional register stores a word in which a bit is to be manipulated. Logic circuitry performs one or more logic operations on the output of the registers whereby a desired bit in said word is manipulated. The output of the logic circuitry may be tested and depending on the result, a jump to a particular instruction stored in the memory may be made.
摘要翻译：一种用于在数字处理器中进行位操作的方法和装置，适用于执行存储在存储器中并根据多个机器周期从所述存储器传送的多个指令，每个所述指令包括操作代码。解码器响应于操作码产生位掩码。生成的位掩码是二进制数字，它是2i的补码，其中i是由操作码的三个最低有效位表示的基数10中的数字。寄存器存储特定的位掩码。一个附加的寄存器存储要处理一个位的字。逻辑电路对寄存器的输出执行一个或多个逻辑运算，从而操纵所述字中的期望位。可以测试逻辑电路的输出，并且根据结果，可以跳转到存储在存储器中的特定指令。

3. 发明授权

US4131944A System bus module for a controller 失效
标题翻译：用于控制器的系统总线模块
公开(公告)号：US4131944A
公开(公告)日：1978-12-26
申请号：US758892
申请日：1977-01-12
申请人： George E. Mager , Frank M. Nelson , Warren L. Hall
发明人： George E. Mager , Frank M. Nelson , Warren L. Hall
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/285
摘要： In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus. The timed protocol unit comprises an address control coupled through the system bus to the central processor for disenabling address signals upon receipt of the first acknowledgement signal on the system bus from the diriment element, and a data control coupled through the system bus to the central processor for bidirectionally disenabling data signals upon receipt of the second acknowledge signal on the system bus from the diriment element.
摘要翻译：在具有通过包括访问数据存储器的数据，地址和控制线的系统总线耦合的中央处理器的控制模块中，包括通过系统总线耦合的直接访问装置，以请求中央处理器的保持并且直接确认通过系统总线访问数据存储器，以指导主机的控制寄存器。还包括连接到中央处理器的连接元件，用于从用于保持请求的直接访问装置接收系统总线上的控制信号，以及从中央处理器传输用于确认的系统总线上的第一和第二控制信号，以及定时协议单元，用于监控在系统总线上传输的数据，地址和控制信号。定时协议单元包括通过系统总线耦合到中央处理器的地址控制器，用于在从系统单元接收到系统总线上的第一确认信号时，使地址信号消失，以及通过系统总线耦合到中央处理器的数据控制用于在从系统元件接收系统总线上的第二应答信号时双向禁用数据信号。

4. 发明授权

US4523299A Message transmitting system for reproduction machines and copiers 失效
标题翻译：复印机和复印机的信息发送系统
公开(公告)号：US4523299A
公开(公告)日：1985-06-11
申请号：US421019
申请日：1982-09-21
申请人： James M. Donohue , Robert E. Markle , George E. Mager , Stephen P. Wilczek
发明人： James M. Donohue , Robert E. Markle , George E. Mager , Stephen P. Wilczek
IPC分类号： G03G21/00 , G03G15/00 , G08C15/00 , G08C15/06 , H04N1/00 , H04N1/32 , G06F9/00
CPC分类号： G03G15/50
摘要： A copy reproduction machine is subdivided into discrete operating modules and coupled together by a shared communication line over which operating messages from and to the modules are transmitted. Each module includes a receiver for intercepting and capturing messages bearing the module's address and a transmitter for transmitting messages from the module and addressed to other modules over the shared communication line.
摘要翻译：复制再现机被细分为离散操作模块，并通过共享通信线路耦合在一起，通过该通信线路发送来自模块和向模块的操作消息。每个模块包括用于拦截和捕获携带模块地址的消息的接收机，以及用于从模块发送消息并通过共享通信线路寻址到其他模块的发射机。

5. 发明授权

US4137565A Direct memory access module for a controller 失效
标题翻译：用于控制器的直接存储器访问模块
公开(公告)号：US4137565A
公开(公告)日：1979-01-30
申请号：US758117
申请日：1977-01-10
申请人： George E. Mager , Frank M. Nelson , Kenneth Gillett , Charles P. Holt , Edward L. Steiner , John W. Daughton , Kenton W. Fiske , Thomas Criswell , Warren L. Hall
发明人： George E. Mager , Frank M. Nelson , Kenneth Gillett , Charles P. Holt , Edward L. Steiner , John W. Daughton , Kenton W. Fiske , Thomas Criswell , Warren L. Hall
IPC分类号： G03G21/14 , G05B19/05 , G06F13/12 , G06F13/28
CPC分类号： G06F13/285 , G05B19/054 , G06F13/124 , G05B2219/1159 , G05B2219/14086 , G05B2219/14144 , G05B2219/15048 , G05B2219/15056
摘要： In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module.
摘要翻译：在诸如具有经由系统总线连接到输入 - 输出处理单元模块的中央处理单元模块的主机的控制器中，作为输入 - 输出处理单元模块的一部分而起作用的直接存储器存取系统通过直接访问中央处理单元模块中的存储器来提供在主机中刷新和更新控制寄存器的高速装置。可以对直接存储器存取系统进行编程，以与其正常模式同步刷新主机设备的控制寄存器，同时异步刷新 - 更新控制寄存器，如在周围的电敏周边的检测到的电气干扰的异常模式控制寄存器，因此需要恢复。通过直接存储器访问系统的高速数据移动是通过在中央处理单元模块中专用随机存取存储器的一部分进行这种访问来实现的，并且将系统总线从中央处理单元模块的控制转移到直接存储器访问系统。这使得能够通过来自专用存储器的固定地址序列访问的数据被直接传送到主机的控制寄存器，而不会产生如果数据由中央处理单元模块中的中央处理器来操纵的时间常数。

6. 发明授权

US4144561A Chip topography for MOS integrated circuitry microprocessor chip 失效
公开(公告)号：US4144561A
公开(公告)日：1979-03-13
申请号：US813902
申请日：1977-07-08
申请人： George K. Tu , Lamar T. Baker , Robert E. Markle , George E. Mager
发明人： George K. Tu , Lamar T. Baker , Robert E. Markle , George E. Mager
IPC分类号： G06F15/78 , H01L27/02 , G06F1/00 , G06F9/00
CPC分类号： H01L27/0207
摘要： The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM. A bus control area is located in the upper right hand corner of the chip. A programmed control area is located between the ALU area and the bus control area in the upper right hand portion of the chip and is coupled to the data bus for receiving instruction words from the program storage area and for generating commands which define the operation of the microprocessor in response to the instruction words. A clock/T-counter is located in the lower right hand corner and is used for synchronizing data signal flow in the micrprocessor. A stack area is located in the lower right hand portion of the chip. Within this stack area are various registers located from top to bottom as follows; write X circuitry, an X register a stack array, stack read/write circuitry, a memory address register, and an incrementer. A stack control is located between the aforementioned stack circuitry and the right hand edge. In addition, a RAM decode is located between the RAM and the left hand edge, a ROM column decode is located between the ROM and the bottom edge, and a ROM row decode is located between the ROM and the stack area.

7. 发明授权

US4141068A Auxiliary ROM memory system 失效
标题翻译：辅助ROM存储系统
公开(公告)号：US4141068A
公开(公告)日：1979-02-20
申请号：US780875
申请日：1977-03-24
申请人： George E. Mager , Frank M. Nelson , Steven L. Reid , Philip Richardson , Vernon E. Rochat , Donald S. Post
发明人： George E. Mager , Frank M. Nelson , Steven L. Reid , Philip Richardson , Vernon E. Rochat , Donald S. Post
IPC分类号： G06F12/06 , G06F9/26 , G06F9/445 , G06F13/00
CPC分类号： G06F8/66 , G06F12/0638
摘要： An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.
摘要翻译：分级的辅助ROM存储器系统，用于提供附加的只读存储器控制程序存储要求的过多或替代提供在基于微处理器的中央处理单元模块上的预定ROM存储器的可能性，以及只读利用可编程只读存储器来加快对ROM位模式的改变的实现/安装的存储器改变能力。可变的PROM存储器包括批量PROM存储器，其包括与现有的板上ROM存储器相互排斥的第一PROM集合，用于可寻址地分支到代码扩展和/或在线代码插入，和/或相互间的第二PROM集合包括存在的板载和即时ROM存储器，用于可解码地寻址大规模代码覆盖。另外，可改变的PROM存储器包括补丁PROM，用于通过多级解码将小规模代码叠加到板上以及用于单列直插位模式改变的偶然ROM存储器中。涉及存储器请求的相互关联的存储器请求被提供给存储器优先级的预定层级以进行解析，这些存储器请求涉及由超过一个存储器类别识别的地址的存储器请求。辅助ROM存储器系统的每个枚举的存储器类别可以操作以使其总体增加或减少，而不使上述寻址层次化。

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