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1. 发明申请

US20130124838A1 INSTRUCTION LEVEL EXECUTION PREEMPTION 审中-公开
标题翻译：指导级执行预防
公开(公告)号：US20130124838A1
公开(公告)日：2013-05-16
申请号：US13294045
申请日：2011-11-10
申请人： Lacky V. SHAH , Gregory Scott Palmer , Gernot Schaufler , Samuel H. Duncan , Philip Browning Johnson , Shirish Gadre , Robert Ohannessian , Nicholas Wang , Christopher Lamb , Philip Alexander Cuadra , Timothy John Purcell
发明人： Lacky V. SHAH , Gregory Scott Palmer , Gernot Schaufler , Samuel H. Duncan , Philip Browning Johnson , Shirish Gadre , Robert Ohannessian , Nicholas Wang , Christopher Lamb , Philip Alexander Cuadra , Timothy John Purcell
IPC分类号： G06F9/38
CPC分类号： G06F9/461
摘要： One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity.
摘要翻译：本发明的一个实施例阐述了技术指令级别和计算线程数组粒度执行抢占。在指令级别抢占不需要处理管道的任何排水。不会发出新的指令，并且从处理流水线中卸载上下文状态。当在计算线程数组边界执行抢占时，由于处理流程内的执行单元完成飞行中指令的执行并变为空闲，因此减少了要存储的上下文状态量。如果完成执行飞行中指令所需的时间超过阈值，则抢占可以动态地改变以在指令级别而不是以计算线程数组粒度来执行。

2. 发明申请

US20130132711A1 COMPUTE THREAD ARRAY GRANULARITY EXECUTION PREEMPTION 审中-公开
标题翻译：计算机螺旋桨阵列精度执行预警
公开(公告)号：US20130132711A1
公开(公告)日：2013-05-23
申请号：US13302962
申请日：2011-11-22
申请人： Lacky V. SHAH , Gregory Scott Palmer , Gernot Schaufler , Samuel H. Duncan , Philip Browning Johnson , Shirish Gadre , Timothy John Purcell
发明人： Lacky V. SHAH , Gregory Scott Palmer , Gernot Schaufler , Samuel H. Duncan , Philip Browning Johnson , Shirish Gadre , Timothy John Purcell
IPC分类号： G06F9/38
CPC分类号： G06F9/461
摘要： One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity.
摘要翻译：本发明的一个实施例阐述了技术指令级别和计算线程数组粒度执行抢占。在指令级别抢占不需要处理管道的任何排水。不会发出新的指令，并且从处理流水线中卸载上下文状态。当在计算线程数组边界执行抢占时，由于处理流程内的执行单元完成飞行中指令的执行并变为空闲，因此减少了要存储的上下文状态量。如果完成执行飞行中指令所需的时间超过阈值，则抢占可以动态地改变以在指令级别而不是以计算线程数组粒度来执行。

3. 发明授权

US09442759B2 Concurrent execution of independent streams in multi-channel time slice groups 有权
标题翻译：在多通道时间片组中并发执行独立流
公开(公告)号：US09442759B2
公开(公告)日：2016-09-13
申请号：US13316334
申请日：2011-12-09
申请人： Samuel H. Duncan , Lacky V. Shah , Sean J. Treichler , Daniel Elliot Wexler , Jerome F. Duluk, Jr. , Philip Browning Johnson , Jonathon Stuart Ramsay Evans
发明人： Samuel H. Duncan , Lacky V. Shah , Sean J. Treichler , Daniel Elliot Wexler , Jerome F. Duluk, Jr. , Philip Browning Johnson , Jonathon Stuart Ramsay Evans
IPC分类号： G06F9/46 , G06F13/00 , G06F9/48 , G06F9/38
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/461
摘要： A time slice group (TSG) is a grouping of different streams of work (referred to herein as “channels”) that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units.
摘要翻译：时间片组（TSG）是共享相同上下文信息的不同工作流（本文称为“信道”）的分组。属于TSG的信道集合以预定的顺序被处理。然而，当通道在处理过程中停顿时，可以切换具有独立工作的下一个通道来完全加载并行处理单元。重要的是，由于TSG中的每个信道共享相同的上下文信息，当TSG中的特定信道的处理停止并且TSG中的下一个信道的处理开始时，不需要上下文切换操作。因此，允许多个独立的工作流在单个上下文中同时运行，增加并行处理单元的利用率。

4. 发明授权

US08698816B2 Graphics processing systems with multiple processors connected in a ring topology 有权
标题翻译：具有连接在环形拓扑中的多个处理器的图形处理系统
公开(公告)号：US08698816B2
公开(公告)日：2014-04-15
申请号：US12979339
申请日：2010-12-28
申请人： Philip Browning Johnson
发明人： Philip Browning Johnson
IPC分类号： G06F15/16 , G06F15/80 , G06F13/14 , G06F13/36 , G06F13/40
CPC分类号： G06F15/17337 , G09G5/363 , G09G2320/0252 , G09G2360/06
摘要： Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.
摘要翻译：图形处理系统中的多个图形处理器以单向或双向环形拓扑互连，允许像素从任何一个图形处理器传输到任何其他图形处理器。系统可以自动识别连接一个或多个监视器的一个或多个“主”图形处理器，并且配置环的链接，使得一个或多个其他图形处理器可以将像素传送到主图形处理器，从而促进分布式呈现操作。系统还可以自动检测图形处理器之间的连接或缺少连接。

5. 发明授权

US07561163B1 Detecting connection topology in a multi-processor graphics system 有权
标题翻译：在多处理器图形系统中检测连接拓扑
公开(公告)号：US07561163B1
公开(公告)日：2009-07-14
申请号：US11305701
申请日：2005-12-16
申请人： Philip Browning Johnson
发明人： Philip Browning Johnson
IPC分类号： G06F15/16 , G06F15/80 , G06F13/14
CPC分类号： G06F15/17337 , G09G5/363 , G09G2320/0252 , G09G2360/06
摘要： Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.
摘要翻译：图形处理系统中的多个图形处理器以单向或双向环形拓扑互连，允许像素从任何一个图形处理器传输到任何其他图形处理器。系统可以自动识别连接一个或多个监视器的一个或多个“主”图形处理器，并且配置环的链接，使得一个或多个其他图形处理器可以将像素传送到主图形处理器，从而促进分布式呈现操作。系统还可以自动检测图形处理器之间的连接或缺少连接。

6. 发明授权

US07042263B1 Memory clock slowdown synthesis circuit 有权
标题翻译：内存时钟减速合成电路
公开(公告)号：US07042263B1
公开(公告)日：2006-05-09
申请号：US10742572
申请日：2003-12-18
申请人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03K3/356
CPC分类号： G06F1/325 , G06F1/08 , G06F1/12 , G06F1/3215
摘要： Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.
摘要翻译：通过产生两个存储器时钟信号来减少图形处理器集成电路上的功率的电路，方法和装置，在一定条件下降低一个频率，并保持另一个的频率。为了减少这两个存储器时钟之间的偏移和抖动，并且为了确保它们保持同相，本发明的示例性实施例使用同步器电路。同步器电路也可用作通用应用时钟发生器。

7. 发明授权

US07525549B1 Display balance/metering 有权
标题翻译：显示平衡/测光
公开(公告)号：US07525549B1
公开(公告)日：2009-04-28
申请号：US11015594
申请日：2004-12-16
申请人： Franck R. Diard , Wayne Douglas Young , Philip Browning Johnson
发明人： Franck R. Diard , Wayne Douglas Young , Philip Browning Johnson
IPC分类号： G06T11/20 , G06F15/80 , G09G5/37
CPC分类号： G06T1/20 , G09G5/39 , G09G2360/06
摘要： Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.
摘要翻译：呈现方法，装置和系统，用于处理使用涉及操作多个图形装置的显示装置进行显示的图像序列，所述显示装置包括处理图像序列中的某些图像的至少一个第一图形装置，包括第一图像，以及至少一个第二图形设备，其处理所述图像序列中的某些其他图像，包括第二图像，所述至少一个第二图形设备对所述第二图像的延迟处理相对于所述第一图像的处理指定的持续时间通过所述至少一个第一图形设备来交错输出所述第一图像的像素数据和为所述第二图像输出的像素数据，并且选择性地将来自所述至少一个第一图形设备和所述至少一个第二图形设备的输出提供给所述显示器设备。

8. 发明申请

US20090085928A1 ANTIALIASING USING MULTIPLE DISPLAY HEADS OF A GRAPHICS PROCESSOR 审中-公开
标题翻译：使用图形处理器的多个显示头进行反射
公开(公告)号：US20090085928A1
公开(公告)日：2009-04-02
申请号：US11680554
申请日：2007-02-28
申请人： Duncan A. Riach , Brijesh Tripathi , Brett T. Hannigan , Philip Browning Johnson
发明人： Duncan A. Riach , Brijesh Tripathi , Brett T. Hannigan , Philip Browning Johnson
IPC分类号： G09G5/00
CPC分类号： G06F3/1431
摘要： Multiple display heads of a single graphics processor are exploited to perform antialiasing and other processing tasks. In one embodiment, two display heads of the same graphics processor are coupled to each other in a master/slave configuration via a pixel transfer path. The “master” display head receives pixels from the “slave” display head in addition to its own pixels, and pixel selection logic in the master display head can blend the two pixels or select either one to the exclusion of the other. If the two pixels correspond to different sampling locations in the same display pixel, the blended pixel is an antialiased pixel.
摘要翻译：利用单个图形处理器的多个显示器头执行抗锯齿和其他处理任务。在一个实施例中，相同图形处理器的两个显示器头经由像素传送路径以主/从配置彼此耦合。 “主”显示头除了其自己的像素之外还从“从”）显示头接收像素，并且主显示头中的像素选择逻辑可以混合两个像素，或者选择一个排除另一个。如果两个像素对应于同一显示像素中的不同采样位置，则混合像素是抗锯齿像素。

9. 发明授权

US09594599B1 Method and system for distributing work batches to processing units based on a number of enabled streaming multiprocessors 有权
标题翻译：基于多个启用的流式多处理器将工作批次分配到处理单元的方法和系统
公开(公告)号：US09594599B1
公开(公告)日：2017-03-14
申请号：US12579143
申请日：2009-10-14
申请人： Philip Browning Johnson , Dale L. Kirkland , Karim M. Abdalla
发明人： Philip Browning Johnson , Dale L. Kirkland , Karim M. Abdalla
IPC分类号： G06F9/46 , G06F9/50 , G06F9/38 , G06F9/48
CPC分类号： G06F9/5083 , G06F9/3851 , G06F9/4843 , G06F9/5027 , G06F9/505 , G06F9/5066 , G06F9/5077
摘要： A work distribution unit distributes work batches to general processing clusters (GPCs) based on the number of streaming multiprocessors included in each GPC. Advantageously, each GPC receives an amount of work that is proportional to the amount of processing power afforded by the GPC. Embodiments include a method for distributing batches of processing tasks to two or more general processing clusters (GPCs), including the steps of updating a counter value for each of the two or more GPCs based on the number of enabled parallel processing units within each of the two or more GPCs, and distributing a batch of processing tasks to a first GPC of the two or more GPCs based on a counter value associated with the first GPC and based on a load signal received from the first GPC.
摘要翻译：工作分配单元基于每个GPC中包括的流式多处理器的数量将工作批次分发到通用处理集群（GPC）。有利地，每个GPC接收与由GPC提供的处理能力的量成比例的一定量的工作。实施例包括用于将批处理任务批处理分配给两个或更多个通用处理集群（GPC）的方法，包括以下步骤：基于每个所述两个或更多个GPC内的所启用的并行处理单元的数目来更新两个或更多个GPC中的每一个的计数器值两个或更多个GPC，并且基于与第一GPC相关联的计数器值并基于从第一GPC接收的负载信号将一批处理任务分配到两个或更多个GPC的第一GPC。

10. 发明授权

US09001134B2 Display balance / metering 有权
标题翻译：显示平衡/测光
公开(公告)号：US09001134B2
公开(公告)日：2015-04-07
申请号：US12418417
申请日：2009-04-03
申请人： Franck R. Diard , Wayne Douglas Young , Philip Browning Johnson
发明人： Franck R. Diard , Wayne Douglas Young , Philip Browning Johnson
IPC分类号： G06F15/16 , G06F15/00 , G06T1/00 , G06T1/20 , G09G5/39
CPC分类号： G06T1/20 , G09G5/39 , G09G2360/06
摘要： Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.
摘要翻译：呈现方法，装置和系统，用于处理使用涉及操作多个图形装置的显示装置进行显示的图像序列，所述显示装置包括处理图像序列中的某些图像的至少一个第一图形装置，包括第一图像，以及至少一个第二图形设备，其处理所述图像序列中的某些其他图像，包括第二图像，所述至少一个第二图形设备对所述第二图像的延迟处理相对于所述第一图像的处理指定的持续时间通过所述至少一个第一图形设备来交错输出所述第一图像的像素数据和为所述第二图像输出的像素数据，并且选择性地将来自所述至少一个第一图形设备和所述至少一个第二图形设备的输出提供给所述显示器设备。

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