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1. 发明授权

US07042263B1 Memory clock slowdown synthesis circuit 有权
标题翻译：内存时钟减速合成电路
公开(公告)号：US07042263B1
公开(公告)日：2006-05-09
申请号：US10742572
申请日：2003-12-18
申请人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03K3/356
CPC分类号： G06F1/325 , G06F1/08 , G06F1/12 , G06F1/3215
摘要： Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.
摘要翻译：通过产生两个存储器时钟信号来减少图形处理器集成电路上的功率的电路，方法和装置，在一定条件下降低一个频率，并保持另一个的频率。为了减少这两个存储器时钟之间的偏移和抖动，并且为了确保它们保持同相，本发明的示例性实施例使用同步器电路。同步器电路也可用作通用应用时钟发生器。

2. 发明申请

US20110191615A1 MEMORY CLOCK SLOWDOWN 有权
标题翻译：内存时钟缓存
公开(公告)号：US20110191615A1
公开(公告)日：2011-08-04
申请号：US12902147
申请日：2010-10-12
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32 , G06F1/12 , G06T1/00 , G06F13/14
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

3. 发明授权

US07187220B1 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US07187220B1
公开(公告)日：2007-03-06
申请号：US10741149
申请日：2003-12-18
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

4. 发明授权

US08707081B2 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US08707081B2
公开(公告)日：2014-04-22
申请号：US12902147
申请日：2010-10-12
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

5. 发明授权

US07836318B1 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US07836318B1
公开(公告)日：2010-11-16
申请号：US11561666
申请日：2006-11-20
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

6. 发明授权

US08495327B2 Memory device synchronization 有权
标题翻译：内存设备同步
公开(公告)号：US08495327B2
公开(公告)日：2013-07-23
申请号：US12794592
申请日：2010-06-04
申请人： Sean Jeffrey Treichler , Barry Alan Wagner
发明人： Sean Jeffrey Treichler , Barry Alan Wagner
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/04 , G06F1/12 , G06F5/06 , G11C7/00
CPC分类号： G06F13/1689
摘要： A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module for providing an internal clock signal and a timing control module for producing a first and second timing control signals. The first and second timing control signals are supplied to the first and second output modules, respectively.
摘要翻译：存储器控制器包括用于驱动第一和第二数据的第一和第二输出模块，以分别写入存储器件。存储器控制器还包括用于提供内部时钟信号的时钟模块和用于产生第一和第二定时控制信号的定时控制模块。第一和第二定时控制信号分别被提供给第一和第二输出模块。

7. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

8. 发明申请

US20110302385A1 MEMORY DEVICE SYNCHRONIZATION 有权
标题翻译：存储器件同步
公开(公告)号：US20110302385A1
公开(公告)日：2011-12-08
申请号：US12794592
申请日：2010-06-04
申请人： Sean Jeffrey Treichler , Barry Alan Wagner
发明人： Sean Jeffrey Treichler , Barry Alan Wagner
IPC分类号： G06F1/04 , G06F1/08 , G06F12/00
CPC分类号： G06F13/1689
摘要： A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module for providing an internal clock signal and a timing control module for producing a first and second timing control signals. The first and second timing control signals are supplied to the first and second output modules, respectively.
摘要翻译：存储器控制器包括用于驱动第一和第二数据的第一和第二输出模块，以分别写入存储器件。存储器控制器还包括用于提供内部时钟信号的时钟模块和用于产生第一和第二定时控制信号的定时控制模块。第一和第二定时控制信号分别被提供给第一和第二输出模块。

9. 发明授权

US07287145B1 System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices 有权
标题翻译：用于回收由相同大小的存储器件组成的存储器中的存储器孔的系统，装置和方法
公开(公告)号：US07287145B1
公开(公告)日：2007-10-23
申请号：US11012006
申请日：2004-12-13
申请人： Brad W. Simeral , Sean Jeffrey Treichler , David G. Reed , Roman Surgutchik
发明人： Brad W. Simeral , Sean Jeffrey Treichler , David G. Reed , Roman Surgutchik
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/0223 , G06F12/06
摘要： A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.
摘要翻译：公开了一种用于增加处理器可访问的物理存储器大小的系统，装置和方法，至少部分地通过回收通常与受限线性地址空间的地址相关联的物理地址空间（即，否则不能由处理器作为系统内存）。在一个实施例中，示例性存储器控制器重定向与一系列地址相关联的线性地址以访问再生存储器孔。存储器控制器包括地址转换器，其被配置为确定受限地址的量并且建立被标识为第一个数字的基准地址，该第一个数字是第一个整数2的幂。地址的范围可以位于被标识为第二个数字的另一个地址第二整数幂为2.因此，地址转换器基于基线地址将线性地址转换为与再生存储器空穴相关联的翻译地址。

10. 发明授权

US07240179B1 System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices 有权
标题翻译：用于回收由任意大小的存储器件组成的存储器中的存储器孔的系统，装置和方法
公开(公告)号：US07240179B1
公开(公告)日：2007-07-03
申请号：US11012025
申请日：2004-12-13
申请人： Sean Jeffrey Treichler , Brad W. Simeral , David G. Reed , Roman Surgutchik
发明人： Sean Jeffrey Treichler , Brad W. Simeral , David G. Reed , Roman Surgutchik
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/023 , G06F12/0292
摘要： A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.
摘要翻译：公开了一种用于增加处理器可访问的物理存储器地址空间的系统，装置和方法，至少部分地通过将与存储器孔相关联的线性地址转换成物理存储器地址的子集，否则该物理存储器地址的子集不能作为系统存储器访问一个处理器在一个实施例中，存储器控制器回收分成线性地址范围的系统存储器中的存储器空间，其中系统存储器包括多个任意大小的存储器件。存储器控制器包括被配置为确定用于存储器孔的转换的存储器孔尺寸的存储器配置评估器，所述存储器孔包括转换为物理地址子集的受限线性地址。此外，存储器配置评估器可以被配置为形成调整的范围，以将至少一个线性地址转换为物理地址的子集。因此，系统存储器至少增加物理地址的子集。

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