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1. 发明申请

US20130124838A1 INSTRUCTION LEVEL EXECUTION PREEMPTION 审中-公开
标题翻译：指导级执行预防
公开(公告)号：US20130124838A1
公开(公告)日：2013-05-16
申请号：US13294045
申请日：2011-11-10
申请人： Lacky V. SHAH , Gregory Scott Palmer , Gernot Schaufler , Samuel H. Duncan , Philip Browning Johnson , Shirish Gadre , Robert Ohannessian , Nicholas Wang , Christopher Lamb , Philip Alexander Cuadra , Timothy John Purcell
发明人： Lacky V. SHAH , Gregory Scott Palmer , Gernot Schaufler , Samuel H. Duncan , Philip Browning Johnson , Shirish Gadre , Robert Ohannessian , Nicholas Wang , Christopher Lamb , Philip Alexander Cuadra , Timothy John Purcell
IPC分类号： G06F9/38
CPC分类号： G06F9/461
摘要： One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity.
摘要翻译：本发明的一个实施例阐述了技术指令级别和计算线程数组粒度执行抢占。在指令级别抢占不需要处理管道的任何排水。不会发出新的指令，并且从处理流水线中卸载上下文状态。当在计算线程数组边界执行抢占时，由于处理流程内的执行单元完成飞行中指令的执行并变为空闲，因此减少了要存储的上下文状态量。如果完成执行飞行中指令所需的时间超过阈值，则抢占可以动态地改变以在指令级别而不是以计算线程数组粒度来执行。

2. 发明申请

US20120110586A1 THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR 有权
标题翻译：用于并行螺纹加工器的螺纹组合调度器
公开(公告)号：US20120110586A1
公开(公告)日：2012-05-03
申请号：US13247819
申请日：2011-09-28
申请人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.
摘要翻译：并行线程处理器执行属于多个协作线程数组（CTA）的线程组。在并行线程处理器的每个周期，指令调度器在随后的周期中选择要发行的线程组以执行。指令调度器通过（i）识别可用线程组的池，（ii）识别具有最大资历值的CTA来选择要执行的线程组，以及（iii）选择具有最大信用值的线程组从具有最高资历价值的CTA内。

3. 发明授权

US08732713B2 Thread group scheduler for computing on a parallel thread processor 有权
标题翻译：线程组调度程序，用于在并行线程处理器上进行计算
公开(公告)号：US08732713B2
公开(公告)日：2014-05-20
申请号：US13247819
申请日：2011-09-28
申请人： Brett W. Coon , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.
摘要翻译：并行线程处理器执行属于多个协作线程数组（CTA）的线程组。在并行线程处理器的每个周期，指令调度器在随后的周期中选择要发行的线程组以执行。指令调度器通过（i）识别可用线程组的池，（ii）识别具有最大资历值的CTA来选择要执行的线程组，以及（iii）选择具有最大信用值的线程组从具有最高资历价值的CTA内。

4. 发明授权

US07730554B2 Double dipped gloves 失效
标题翻译：双手套
公开(公告)号：US07730554B2
公开(公告)日：2010-06-08
申请号：US11203921
申请日：2005-08-12
申请人： Nicholas Wang
发明人： Nicholas Wang
IPC分类号： A41D19/00 , B29D22/00 , B29D23/00 , B32B1/00 , B32B27/00 , B32B27/08
CPC分类号： B32B25/14 , A41D19/0058 , Y10S2/901 , Y10T428/13 , Y10T428/1352 , Y10T428/24942 , Y10T428/31917
摘要： A method of making a glove is described. The method comprises dipping a glove form into two different formulations. Each formulation comprises a carboxylated nitrile butadiene rubber with different amounts of covalent and ionic cross linkers. The gloves preferably have a stress retention value of greater than 50%.
摘要翻译：描述制作手套的方法。该方法包括将手套形式浸入两种不同的配方中。每种制剂包含具有不同量的共价和离子交联剂的羧化丁腈橡胶。手套优选具有大于50％的应力保持值。

5. 发明授权

US09850398B2 Powderless coating polymer and powderless glove comprising the same 有权
公开(公告)号：US09850398B2
公开(公告)日：2017-12-26
申请号：US14826714
申请日：2015-08-14
申请人： Nicholas Wang
发明人： Nicholas Wang
IPC分类号： C09D147/00 , A41D19/00 , C08K5/00 , C08K3/22 , C08K5/47 , C08K5/39 , C08K3/30
CPC分类号： C09D147/00 , A41D19/0055 , C08K3/22 , C08K3/30 , C08K5/0025 , C08K5/39 , C08K5/47 , C08K2003/2296 , C08L13/02 , C08L69/00
摘要： The present invention provides a powder-free polymeric coating comprising a latex polymer, a metal oxide and a cross-linking agent, the latex polymer comprising a diene and an acrylic acid; and a powder-free glove comprising the powderless coating polymer.

6. 发明授权

US09110810B2 Multi-level instruction cache prefetching 有权
标题翻译：多级指令缓存预取
公开(公告)号：US09110810B2
公开(公告)日：2015-08-18
申请号：US13312962
申请日：2011-12-06
申请人： Nicholas Wang , Jack Hilaire Choquette
发明人： Nicholas Wang , Jack Hilaire Choquette
IPC分类号： G06F13/00 , G06F13/28 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/3875 , G06F2212/6026
摘要： One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache 370 is located within the first sector of the corresponding L1.5 cache line, then the selected prefetch target is located at a sector within the next L1.5 cache line. The result is that the instruction L1 cache hit rate is improved and instruction fetch latency is reduced, even where the processor consumes instructions in the instruction L1 cache at a fast rate.
摘要翻译：本发明的一个实施例提出了一种改进的方式来预取多级缓存中的指令。提取单元基于伪随机数发生器的功能和与当前指令L1高速缓存行相对应的扇区，发起预取操作以传送一组多个高速缓存行中的一个。提取单元根据一些概率函数从多条高速缓存行集合中选择预取目标。如果当前指令L1高速缓存370位于对应的L1.5高速缓存行的第一扇区内，则所选择的预取目标位于下一个L1.5高速缓存行内的扇区处。结果是，即使在处理器以快速的速率消耗指令L1高速缓存中的指令的情况下，指令L1高速缓存命中率得到改善并且指令提取延迟被降低。

7. 发明申请

US20130145102A1 MULTI-LEVEL INSTRUCTION CACHE PREFETCHING 有权
标题翻译：多级指导高速缓存
公开(公告)号：US20130145102A1
公开(公告)日：2013-06-06
申请号：US13312962
申请日：2011-12-06
申请人： Nicholas Wang , Jack Hilaire Choquette
发明人： Nicholas Wang , Jack Hilaire Choquette
IPC分类号： G06F12/02
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/3875 , G06F2212/6026
摘要： One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache 370 is located within the first sector of the corresponding L1.5 cache line, then the selected prefetch target is located at a sector within the next L1.5 cache line. The result is that the instruction L1 cache hit rate is improved and instruction fetch latency is reduced, even where the processor consumes instructions in the instruction L1 cache at a fast rate.
摘要翻译：本发明的一个实施例提出了一种改进的方式来预取多级缓存中的指令。提取单元基于伪随机数发生器的功能和与当前指令L1高速缓存行相对应的扇区，发起预取操作以传送一组多个高速缓存行中的一个。提取单元根据一些概率函数从多条高速缓存行集合中选择预取目标。如果当前指令L1高速缓存370位于对应的L1.5高速缓存行的第一扇区内，则所选择的预取目标位于下一个L1.5高速缓存行内的扇区处。结果是，即使在处理器以快速的速率消耗指令L1高速缓存中的指令的情况下，指令L1高速缓存命中率得到改善并且指令提取延迟被降低。

8. 发明申请

US20070033704A1 Double dipped gloves 失效
标题翻译：双手套
公开(公告)号：US20070033704A1
公开(公告)日：2007-02-15
申请号：US11203921
申请日：2005-08-12
申请人： Nicholas Wang
发明人： Nicholas Wang
IPC分类号： B32B25/04 , B32B25/16 , A41D19/00
CPC分类号： B32B25/14 , A41D19/0058 , Y10S2/901 , Y10T428/13 , Y10T428/1352 , Y10T428/24942 , Y10T428/31917
摘要： A method of making a glove is described. The method comprises dipping a glove form into two different formulations. Each formulation comprises a carboxylated nitrile butadiene rubber with different amounts of covalent and ionic cross linkers. The gloves preferably have a stress retention value of greater than 50%.
摘要翻译：描述制作手套的方法。该方法包括将手套形式浸入两种不同的配方中。每种制剂包括具有不同量的共价和离子交联剂的羧化丁腈橡胶。手套优选具有大于50％的应力保持值。

9. 发明授权

US08522000B2 Trap handler architecture for a parallel processing unit 有权
标题翻译：并行处理单元的陷阱处理器架构
公开(公告)号：US08522000B2
公开(公告)日：2013-08-27
申请号：US12569831
申请日：2009-09-29
申请人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
发明人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

10. 发明申请

US20110078427A1 TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT 有权
标题翻译：并行处理单元的TRAP操作架构
公开(公告)号：US20110078427A1
公开(公告)日：2011-03-31
申请号：US12569831
申请日：2009-09-29
申请人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
发明人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

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