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1. 发明申请

US20150079757A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150079757A1
公开(公告)日：2015-03-19
申请号：US14299287
申请日：2014-06-09
申请人： Kyung-Yub JEON , Jun-ho YOON , Min-joon PARK
发明人： Kyung-Yub JEON , Jun-ho YOON , Min-joon PARK
IPC分类号： H01L21/033 , H01L49/02 , H01L21/768 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31144 , H01L21/32155 , H01L21/76814 , H01L21/76816 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/11524 , H01L27/11556 , H01L28/91
摘要： A method of fabricating a semiconductor device is provided and includes forming one or more molding layers on a substrate, forming a silicon mask layer, first and second mask layers, and a mask pattern having a different etch selectivity to be vertically aligned on the molding layer, patterning the second mask layer with a second mask pattern using the mask pattern as an etching mask, patterning the first mask layer with a first mask pattern using the second mask pattern as an etching mask, patterning the silicon mask layer with a silicon mask pattern using the first mask pattern as an etching mask, changing the silicon mask pattern to a hard mask pattern having an improved etch selectivity by doping impurities into the silicon mask pattern, forming a hole having a high aspect ratio contact (HARC) structure vertically passing through the molding layer using the hard mask pattern as an etching mask, and removing the hard mask pattern.
摘要翻译：提供了一种制造半导体器件的方法，包括在衬底上形成一个或多个成型层，形成硅掩模层，第一和第二掩模层以及具有不同蚀刻选择性的掩模图案，以在成型层上垂直对准使用掩模图案作为蚀刻掩模用第二掩模图案对第二掩模层进行构图，使用第二掩模图案将第一掩模图案作为蚀刻掩模，用硅掩模图案图案化硅掩模层使用第一掩模图案作为蚀刻掩模，通过将杂质掺杂到硅掩模图案中将硅掩模图案改变为具有改善的蚀刻选择性的硬掩模图案，形成垂直穿过的高纵横比接触（HARC）结构的孔使用硬掩模图案作为蚀刻掩模的成型层，以及去除硬掩模图案。

2. 发明申请

US20120064709A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20120064709A1
公开(公告)日：2012-03-15
申请号：US13216051
申请日：2011-08-23
申请人： Kyung-Yub JEON , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人： Kyung-Yub JEON , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法。该方法可以包括在半导体衬底上形成第一绝缘层。可以在第一绝缘层上形成第一多晶硅层。可以在第一多晶硅层上形成第二绝缘层。可以在第二绝缘层上形成第二多晶硅层。可以在第二多晶硅层上形成掩模图案。可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成暴露第二绝缘层的一部分的第二多晶硅图案。第二多晶硅图案的侧壁可以包括第一非晶区域。第一非晶区域可以通过第一次重结晶过程结晶。可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

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