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1. 发明授权

US09240441B2 Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode 有权
标题翻译：包括用于电极的支撑体的半导体器件和形成包括电极支撑体的半导体器件的方法
公开(公告)号：US09240441B2
公开(公告)日：2016-01-19
申请号：US13966328
申请日：2013-08-14
申请人： Junho Yoon , Gyungjin Min , Jaehong Park , Yongmoon Jang , Je-Woo Han
发明人： Junho Yoon , Gyungjin Min , Jaehong Park , Yongmoon Jang , Je-Woo Han
IPC分类号： H01L21/8239 , H01L49/02
CPC分类号： H01L28/60 , H01L28/40 , H01L28/56 , H01L28/91 , H01L28/92
摘要： Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes.
摘要翻译：提供半导体器件。每个半导体器件可以包括多个电极。此外，每个半导体器件可以包括连接到多个电极的侧壁的支撑图案。还提供了形成半导体器件的相关方法。例如，所述方法可以包括在形成多个电极之前形成支撑图案。

2. 发明申请

US20150056805A1 METHODS OF FORMING SEMICONDUCTOR DEVICE USING BOWING CONTROL LAYER 有权
标题翻译：使用控制层形成半导体器件的方法
公开(公告)号：US20150056805A1
公开(公告)日：2015-02-26
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

3. 发明申请

US20080070417A1 Method of etching semiconductor device and method of fabricating semiconductor device using the same 审中-公开
标题翻译：半导体器件的蚀刻方法及使用其制造半导体器件的方法
公开(公告)号：US20080070417A1
公开(公告)日：2008-03-20
申请号：US11827450
申请日：2007-07-12
申请人： Je-woo Han , Myeong-cheol Kim , Dong-hyun Kim
发明人： Je-woo Han , Myeong-cheol Kim , Dong-hyun Kim
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L27/105 , H01L27/11568 , H01L29/40117
摘要： A method of fabricating a semiconductor device which prevents a pitting phenomenon from occurring on a gate insulating layer is provided. The method of fabricating of a semiconductor device according to the present invention comprises: depositing a first gate material including at least a gate insulating layer and a first metal layer in a first region on a semiconductor substrate; depositing a second gate material layer including at least a gate insulating layer and a polysilicon layer in a second region on the semiconductor substrate; forming a hard mask pattern on the first gate material layer and on the second gate material layer; and forming a first gate pattern and a second gate pattern by etching the first gate material layer and the second gate material layer, using the hard mask pattern as a mask, wherein the step of forming the first gate pattern and the second gate pattern comprises dry etching the first metal layer and the polysilicon layer simultaneously using a first etching gas composition including both CF4 and CH4, such that when the first metal layer is completely etched, a polysilicon layer of at least a predetermined minimum protective thickness remains covering the underlying gate insulating layer. The etch rate of the first metal layer to the etch rate of polysilicon can be relatively increased by the method of this invention, and, as a result, a gate pattern with high density can be effectively formed.
摘要翻译：提供一种制造半导体器件的方法，该方法防止在栅极绝缘层上发生点蚀现象。根据本发明的制造半导体器件的方法包括：在半导体衬底上的第一区域中沉积包括至少栅极绝缘层和第一金属层的第一栅极材料; 在所述半导体衬底上的第二区域中沉积包括至少栅极绝缘层和多晶硅层的第二栅极材料层; 在第一栅极材料层和第二栅极材料层上形成硬掩模图案; 以及通过使用所述硬掩模图案作为掩模蚀刻所述第一栅极材料层和所述第二栅极材料层来形成第一栅极图案和第二栅极图案，其中形成所述第一栅极图案和所述第二栅极图案的步骤包括干燥使用包括CF 4和CH 4 4的第一蚀刻气体组合物同时蚀刻第一金属层和多晶硅层，使得当第一金属层被完全蚀刻时，至少预定的最小保护厚度的多晶硅层保持覆盖下面的栅极绝缘层。通过本发明的方法，可以相对增加第一金属层对多晶硅的蚀刻速率的蚀刻速率，结果可以有效地形成高密度的栅极图案。

4. 发明授权

US08815697B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815697B2
公开(公告)日：2014-08-26
申请号：US13478450
申请日：2012-05-23
申请人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
发明人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
IPC分类号： H01L21/3213 , H01L27/108 , H01L21/285
CPC分类号： H01L28/90 , H01L27/10852
摘要： Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
摘要翻译：提供一种制造具有电容器的半导体器件的方法。该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。形成贯穿复合层的多个开口。在多个开口中形成下电极。去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。在下电极上形成介电层，在电介质层上形成上电极。

5. 发明申请

US20130005110A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130005110A1
公开(公告)日：2013-01-03
申请号：US13478450
申请日：2012-05-23
申请人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
发明人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
IPC分类号： H01L21/02
CPC分类号： H01L28/90 , H01L27/10852
摘要： Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
摘要翻译：提供一种制造具有电容器的半导体器件的方法。该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。形成贯穿复合层的多个开口。在多个开口中形成下电极。去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。在下电极上形成介电层，在电介质层上形成上电极。

6. 发明申请

US20160093686A1 SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE 审中-公开
标题翻译：包括用于电极的支持的半导体器件和形成包括用于电极的支持的半导体器件的方法
公开(公告)号：US20160093686A1
公开(公告)日：2016-03-31
申请号：US14961994
申请日：2015-12-08
申请人： Junho Yoon , Gyungjin Min , Jaehong Park , Yongmoon Jang , Je-Woo Han
发明人： Junho Yoon , Gyungjin Min , Jaehong Park , Yongmoon Jang , Je-Woo Han
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L28/40 , H01L28/56 , H01L28/91 , H01L28/92
摘要： Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes.
摘要翻译：提供半导体器件。每个半导体器件可以包括多个电极。此外，每个半导体器件可以包括连接到多个电极的侧壁的支撑图案。还提供了形成半导体器件的相关方法。例如，所述方法可以包括在形成多个电极之前形成支撑图案。

7. 发明授权

US09093500B2 Methods of forming semiconductor device using bowing control layer 有权
标题翻译：使用弯曲控制层形成半导体器件的方法
公开(公告)号：US09093500B2
公开(公告)日：2015-07-28
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

8. 发明授权

US08822341B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08822341B2
公开(公告)日：2014-09-02
申请号：US13164090
申请日：2011-06-20
申请人： Yong-Ho Jeon , Dong-Hyun Kim , Je-Woo Han , Kyoung-Sub Shin
发明人： Yong-Ho Jeon , Dong-Hyun Kim , Je-Woo Han , Kyoung-Sub Shin
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/768
CPC分类号： H01L21/30655 , H01L21/76898
摘要： A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.
摘要翻译：用于等离子体蚀刻的第一气体和用于等离子体沉积的第二气体被引入到半导体衬底上，该半导体衬底包括掩模图案。第一气体和第二气体的流量在处理循环期间的流量范围内周期性地变化，使得等离子体蚀刻工艺和等离子体沉积工艺一起进行以在半导体衬底中形成开口。

9. 发明授权

US08563371B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08563371B2
公开(公告)日：2013-10-22
申请号：US13216051
申请日：2011-08-23
申请人： Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人： Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号： H01L21/84 , H01L21/00 , H01L21/8238 , H01L21/461 , H01L21/302
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法。该方法可以包括在半导体衬底上形成第一绝缘层。可以在第一绝缘层上形成第一多晶硅层。可以在第一多晶硅层上形成第二绝缘层。可以在第二绝缘层上形成第二多晶硅层。可以在第二多晶硅层上形成掩模图案。可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成露出第二绝缘层的一部分的第二多晶硅图案。第二多晶硅图案的侧壁可以包括第一非晶区域。第一非晶区域可以通过第一次重结晶过程结晶。可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

10. 发明申请

US20120164809A1 SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES 审中-公开
标题翻译：包括应变半导体区域的半导体器件，其制造方法以及包括器件的电子系统
公开(公告)号：US20120164809A1
公开(公告)日：2012-06-28
申请号：US13298732
申请日：2011-11-17
申请人： Jun-Ho YOON , Kyoung-Sub SHIN , Jin-Wook LEE , Je-Woo HAN , Hyung-Yong KIM
发明人： Jun-Ho YOON , Kyoung-Sub SHIN , Jin-Wook LEE , Je-Woo HAN , Hyung-Yong KIM
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/30608 , H01L21/3065 , H01L21/32137 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅极图案，通过将含有IV或VIII族元素的掺杂剂注入到半导体衬底的部分中形成与栅极图案相邻的非晶硅（a-Si）区域，形成在栅极图案的侧壁上的栅极间隔物，通过使用第一蚀刻工艺蚀刻a-Si区域和衬底形成第一腔体，通过蚀刻衬底形成第二腔体，使得第二腔体扩展第一腔体的轮廓在横向和垂直方向上，并在第二腔中形成应变半导体区域。

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