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1. 发明授权

US09093500B2 Methods of forming semiconductor device using bowing control layer 有权
标题翻译：使用弯曲控制层形成半导体器件的方法
公开(公告)号：US09093500B2
公开(公告)日：2015-07-28
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

2. 发明申请

US20150079757A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150079757A1
公开(公告)日：2015-03-19
申请号：US14299287
申请日：2014-06-09
申请人： Kyung-Yub JEON , Jun-ho YOON , Min-joon PARK
发明人： Kyung-Yub JEON , Jun-ho YOON , Min-joon PARK
IPC分类号： H01L21/033 , H01L49/02 , H01L21/768 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31144 , H01L21/32155 , H01L21/76814 , H01L21/76816 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/11524 , H01L27/11556 , H01L28/91
摘要： A method of fabricating a semiconductor device is provided and includes forming one or more molding layers on a substrate, forming a silicon mask layer, first and second mask layers, and a mask pattern having a different etch selectivity to be vertically aligned on the molding layer, patterning the second mask layer with a second mask pattern using the mask pattern as an etching mask, patterning the first mask layer with a first mask pattern using the second mask pattern as an etching mask, patterning the silicon mask layer with a silicon mask pattern using the first mask pattern as an etching mask, changing the silicon mask pattern to a hard mask pattern having an improved etch selectivity by doping impurities into the silicon mask pattern, forming a hole having a high aspect ratio contact (HARC) structure vertically passing through the molding layer using the hard mask pattern as an etching mask, and removing the hard mask pattern.
摘要翻译：提供了一种制造半导体器件的方法，包括在衬底上形成一个或多个成型层，形成硅掩模层，第一和第二掩模层以及具有不同蚀刻选择性的掩模图案，以在成型层上垂直对准使用掩模图案作为蚀刻掩模用第二掩模图案对第二掩模层进行构图，使用第二掩模图案将第一掩模图案作为蚀刻掩模，用硅掩模图案图案化硅掩模层使用第一掩模图案作为蚀刻掩模，通过将杂质掺杂到硅掩模图案中将硅掩模图案改变为具有改善的蚀刻选择性的硬掩模图案，形成垂直穿过的高纵横比接触（HARC）结构的孔使用硬掩模图案作为蚀刻掩模的成型层，以及去除硬掩模图案。

3. 发明授权

US08563371B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08563371B2
公开(公告)日：2013-10-22
申请号：US13216051
申请日：2011-08-23
申请人： Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人： Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号： H01L21/84 , H01L21/00 , H01L21/8238 , H01L21/461 , H01L21/302
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法。该方法可以包括在半导体衬底上形成第一绝缘层。可以在第一绝缘层上形成第一多晶硅层。可以在第一多晶硅层上形成第二绝缘层。可以在第二绝缘层上形成第二多晶硅层。可以在第二多晶硅层上形成掩模图案。可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成露出第二绝缘层的一部分的第二多晶硅图案。第二多晶硅图案的侧壁可以包括第一非晶区域。第一非晶区域可以通过第一次重结晶过程结晶。可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

4. 发明授权

US08426274B2 Method of forming recess and method of manufacturing semiconductor device having the same 有权
标题翻译：形成凹部的方法和制造其的半导体器件的制造方法
公开(公告)号：US08426274B2
公开(公告)日：2013-04-23
申请号：US12861247
申请日：2010-08-23
申请人： Jun-Ho Yoon , Kyoung-Sub Shin , Sung-Sam Lee , Kung-Hyon Nam , Hong Cho , Joon-Seok Moon
发明人： Jun-Ho Yoon , Kyoung-Sub Shin , Sung-Sam Lee , Kung-Hyon Nam , Hong Cho , Joon-Seok Moon
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/02238 , H01L21/3065 , H01L29/66621
摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.
摘要翻译：示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。该方法包括形成在衬底中限定有源区的场区域。有源区在衬底中沿第一方向延伸。所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍牺牲氧化层。

5. 发明申请

US20120164809A1 SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES 审中-公开
标题翻译：包括应变半导体区域的半导体器件，其制造方法以及包括器件的电子系统
公开(公告)号：US20120164809A1
公开(公告)日：2012-06-28
申请号：US13298732
申请日：2011-11-17
申请人： Jun-Ho YOON , Kyoung-Sub SHIN , Jin-Wook LEE , Je-Woo HAN , Hyung-Yong KIM
发明人： Jun-Ho YOON , Kyoung-Sub SHIN , Jin-Wook LEE , Je-Woo HAN , Hyung-Yong KIM
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/30608 , H01L21/3065 , H01L21/32137 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅极图案，通过将含有IV或VIII族元素的掺杂剂注入到半导体衬底的部分中形成与栅极图案相邻的非晶硅（a-Si）区域，形成在栅极图案的侧壁上的栅极间隔物，通过使用第一蚀刻工艺蚀刻a-Si区域和衬底形成第一腔体，通过蚀刻衬底形成第二腔体，使得第二腔体扩展第一腔体的轮廓在横向和垂直方向上，并在第二腔中形成应变半导体区域。

6. 发明授权

US08274578B2 Gaze tracking apparatus and method using difference image entropy 有权
标题翻译：凝视跟踪装置和使用差分图像熵的方法
公开(公告)号：US08274578B2
公开(公告)日：2012-09-25
申请号：US12368269
申请日：2009-02-09
申请人： Kwang Seok Hong , Jun Ho Yoon , Jong Bae Jeon , Kue Bum Lee
发明人： Kwang Seok Hong , Jun Ho Yoon , Jong Bae Jeon , Kue Bum Lee
IPC分类号： H04N5/228
CPC分类号： G06F3/013 , G06K9/00335 , G06T7/248
摘要： In accordance with one aspect of the present invention, there is provided a gaze tracking apparatus using difference image entropy, comprising: image detection module for detecting user's eye region image from image of the user taken by picture-taking apparatus which is connected to the gaze tracking apparatus; image selection module for computing entropy value of difference image between the eye region image and a plurality of reference images respectively indicating each gazing direction and selecting reference image with least difference image entropy value among the plurality of reference images; and gaze tracking module for recognizing user's gazing direction by regarding gazing direction that the selected reference image indicates as user's gazing direction.
摘要翻译：根据本发明的一个方面，提供了一种使用差分图像熵的注视跟踪装置，包括：图像检测模块，用于从连接到注视的摄像装置拍摄的用户的图像中检测用户的眼睛区域图像跟踪装置图像选择模块，用于计算眼睛区域图像和多个参考图像之间的差分图像的熵值，所述参考图像分别指示多个参考图像中的每个注视方向和选择具有最小差异图像熵值的参考图像; 以及注视跟踪模块，用于通过将所选择的参考图像指示为用户的注视方向的注视方向来识别用户的注视方向。

7. 发明申请

US20120064709A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20120064709A1
公开(公告)日：2012-03-15
申请号：US13216051
申请日：2011-08-23
申请人： Kyung-Yub JEON , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人： Kyung-Yub JEON , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法。该方法可以包括在半导体衬底上形成第一绝缘层。可以在第一绝缘层上形成第一多晶硅层。可以在第一多晶硅层上形成第二绝缘层。可以在第二绝缘层上形成第二多晶硅层。可以在第二多晶硅层上形成掩模图案。可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成暴露第二绝缘层的一部分的第二多晶硅图案。第二多晶硅图案的侧壁可以包括第一非晶区域。第一非晶区域可以通过第一次重结晶过程结晶。可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

8. 发明申请

US20110053327A1 METHOD OF FORMING RECESS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE SAME 有权
标题翻译：形成记忆的方法和制造其相同的半导体器件的方法
公开(公告)号：US20110053327A1
公开(公告)日：2011-03-03
申请号：US12861247
申请日：2010-08-23
申请人： Jun-Ho YOON , Kyoung-Sub Shin , Sung-Sam Lee , Kung-Hyon Nam , Hong Cho , Joon-Seok Moon
发明人： Jun-Ho YOON , Kyoung-Sub Shin , Sung-Sam Lee , Kung-Hyon Nam , Hong Cho , Joon-Seok Moon
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/02238 , H01L21/3065 , H01L29/66621
摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.
摘要翻译：示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。该方法包括形成在衬底中限定有源区的场区域。有源区域在衬底中沿第一方向延伸。所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍牺牲氧化层。

9. 发明申请

US20060143321A1 Apparatus and method for managing peripheral device using auto-generated metadata 审中-公开
标题翻译：使用自动生成元数据管理外围设备的装置和方法
公开(公告)号：US20060143321A1
公开(公告)日：2006-06-29
申请号：US11290443
申请日：2005-12-01
申请人： Jun-Ho Yoon
发明人： Jun-Ho Yoon
IPC分类号： G06F3/00
CPC分类号： H04L67/125
摘要： A peripheral device managing apparatus using auto-generated metadata and method of using the same are provided. The peripheral device managing apparatus includes a plurality of peripheral devices for generating execution data by executing a function of the peripheral device, and generating metadata which includes identification information of the execution data, a plurality of peripheral device controlling units for respectively controlling the peripheral devices through a network, and generating management data by adding the metadata to the execution data, and a peripheral device managing unit for storing the generated management data, and retrieving management data which meets a predetermined search condition out of the management data. Accordingly, a plurality of peripheral devices and a plurality of peripheral device controlling units can be efficiently managed.
摘要翻译：提供了使用自动生成元数据的外围设备管理装置及其使用方法。外围设备管理设备包括多个外围设备，用于通过执行外围设备的功能来生成执行数据，并且生成包括执行数据的识别信息的元数据，多个外围设备控制单元，用于分别控制外围设备通过网络，以及通过将元数据添加到执行数据来生成管理数据;以及外围设备管理单元，用于存储生成的管理数据，以及从管理数据中检索满足预定搜索条件的管理数据。因此，可以有效地管理多个外围设备和多个外围设备控制单元。

10. 发明授权

US08815697B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815697B2
公开(公告)日：2014-08-26
申请号：US13478450
申请日：2012-05-23
申请人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
发明人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
IPC分类号： H01L21/3213 , H01L27/108 , H01L21/285
CPC分类号： H01L28/90 , H01L27/10852
摘要： Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
摘要翻译：提供一种制造具有电容器的半导体器件的方法。该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。形成贯穿复合层的多个开口。在多个开口中形成下电极。去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。在下电极上形成介电层，在电介质层上形成上电极。

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