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    • 1. 发明申请
    • Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock
    • 使用电压升压时钟的单功率晶体管电池充电电路
    • US20110267008A1
    • 2011-11-03
    • US13179107
    • 2011-07-08
    • Kwok Kuen KwongYat To WongHo Ming (Karen) WanChik Wai Ng
    • Kwok Kuen KwongYat To WongHo Ming (Karen) WanChik Wai Ng
    • H02J7/00
    • H02J7/0031
    • A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
    • 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点,以关闭功率晶体管,从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压,并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关,其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。
    • 2. 发明申请
    • Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock
    • 使用电压升压时钟的单功率晶体管电池充电电路
    • US20100148727A1
    • 2010-06-17
    • US12336514
    • 2008-12-16
    • Kwok Kuen KwongYat To WongHo Ming (Karen) WanChik Wai Ng
    • Kwok Kuen KwongYat To WongHo Ming (Karen) WanChik Wai Ng
    • H02J7/00
    • H02J7/0031
    • A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
    • 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点,以关闭功率晶体管,从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压,并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关,其将升压电压的时钟驱动到栅极耦合晶体管的栅极,以关断功率晶体管。
    • 3. 发明申请
    • ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs
    • 使用电容耦合钳位保护低压芯片晶体管的ESD保护从高压输出
    • US20100315748A1
    • 2010-12-16
    • US12481696
    • 2009-06-10
    • Kwok Kuen KwongChik Wai NgWai Kit (Victor) SOHing Kit KWAN
    • Kwok Kuen KwongChik Wai NgWai Kit (Victor) SOHing Kit KWAN
    • H02H9/00
    • H03K19/00315H01L27/0266H03K19/018557
    • An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
    • 静电放电(ESD)保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。 栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源,并在供电时禁用ESD保护电路。 施加到输出端的ESD脉冲通过ESD耦合电容器耦合,使耦合栅极节点高电压,并接通栅极 - 接地晶体管,使n沟道输出晶体管的栅极接地,从而分解ESD电流。 防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。
    • 4. 发明申请
    • Low Voltage High-Output-Driving CMOS Voltage Reference With Temperature Compensation
    • 具有温度补偿功能的低电压高输出驱动CMOS参考电压
    • US20100073070A1
    • 2010-03-25
    • US12237500
    • 2008-09-25
    • Chik Wai NgKwok Kuen Kwong
    • Chik Wai NgKwok Kuen Kwong
    • G05F1/567G05F1/10
    • G05F3/30
    • A bandgap reference voltage generator has a first stage that generates a first current that is complementary-to-absolute-temperature (Ictat) and a second stage that generates a current that is proportional-to-absolute-temperature (Iptat). The Ictat and Iptat currents are both forced through a summing resistor to generate a voltage that is relatively independent of temperature, since the Ictat and Iptat currents cancel out each other's temperature dependencies. A PMOS output transistor drives current to an output load to maintain the load at the reference voltage. An op amp drives the gate of the PMOS output transistor and has inputs connected to emitters of PNP transistors in the second stage. A series of resistors generate the reference voltage between the PMOS output transistor and ground and drives bases of the PNP transistors and includes the summing resistor. Parasitic PNP transistors in an all-CMOS process are used. The generator operates with a 1-volt power supply.
    • 带隙参考电压发生器具有产生互补绝对温度(Ictat)的第一电流的第一级和产生与绝对温度成比例的电流(Iptat)的第二级。 Ictat和Iptat电流都被强制通过求和电阻产生一个相对独立于温度的电压,因为Ictat和Iptat电流抵消了彼此的温度依赖性。 PMOS输出晶体管将电流驱动到输出负载以将负载保持在参考电压。 运算放大器驱动PMOS输出晶体管的栅极,并且在第二级中具有连接到PNP晶体管的发射极的输入。 一系列电阻器在PMOS输出晶体管和地之间产生参考电压,并驱动PNP晶体管的基极,并包含求和电阻。 使用全CMOS工艺中的寄生PNP晶体管。 发电机采用1伏电源供电。
    • 7. 发明申请
    • Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter
    • 恒流控制模块使用变频滤波乘法器进行离线电流模式初级侧检测隔离反激式转换器
    • US20110216559A1
    • 2011-09-08
    • US12718707
    • 2010-03-05
    • Chik Wai (David) NgHing Kit KwanPo Wah ChangWai Kit (Victor) SoKwok Kuen Kwong
    • Chik Wai (David) NgHing Kit KwanPo Wah ChangWai Kit (Victor) SoKwok Kuen Kwong
    • H02M3/335
    • H02M3/335
    • A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.
    • 回扫AC-DC电力转换器具有恒定电流控制回路,其感测变压器中的主要输出电流,以在没有昂贵的光隔离器的情况下控制次级输出。 初级侧控制电路可以使用准谐振(QR)或脉冲宽度调制(PWM)控制回路来切换通过变压器的一次电流的开和关。 将反馈电压与从初级电流回路感测的初级侧电压进行比较,以打开和关闭开关。 乘法器环路使用乘法器产生反馈电压。 电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器,以产生滤波电压。 高增益误差放大器将滤波电压与参考电压进行比较,以产生反馈电压。 乘法器产生二次电流和参考电压之间的简单关系,产生简化的电流控制。