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1. 发明授权

US5248384A Rapid thermal treatment to eliminate metal void formation in VLSI manufacturing process 失效
标题翻译：快速热处理以消除VLSI制造过程中的金属空隙形成
公开(公告)号：US5248384A
公开(公告)日：1993-09-28
申请号：US803518
申请日：1991-12-09
申请人： Kwang-Ming Lin , Lih-Shyng Tsai , Jiunn-Jyi Lin , Chin-Twan Wei
发明人： Kwang-Ming Lin , Lih-Shyng Tsai , Jiunn-Jyi Lin , Chin-Twan Wei
IPC分类号： H01L21/321
CPC分类号： H01L21/321
摘要： The method of forming a void-free surface on aluminum-copper metallurgy after stripping of resist is described. There is provided an aluminum-copper metallurgy on a suitable substrate, such as a semiconductor integrated circuit wafer during manufacture. A resist layer is formed over surface. The resist layer is exposing, developing and the developed resist is used as an etch mask to etch a layer, such as an insulating layer on the metallurgy which results in exposing the aluminum-copper metallurgy surface. The resist etch mask is removed by plasma oxygen ashing in presence of the exposed aluminum-copper surface. Rapid thermal annealing of the aluminum-copper metallurgy at a temperature of between about 400.degree. to 550.degree. C. is performed. The resulting surfaces are rinsed to remove any residual resist material. The result is a void-free aluminum-copper metallurgy surface.
摘要翻译：描述了剥离抗蚀剂后在铝 - 铜冶金学上形成无空隙表面的方法。在合适的基板上提供铝 - 铜冶金，例如在制造期间的半导体集成电路晶片。在表面上形成抗蚀剂层。抗蚀剂层是曝光，显影，并且显影的抗蚀剂用作蚀刻掩模以蚀刻诸如在冶金学上的绝缘层的层，这导致暴露铝 - 铜冶金表面。在暴露的铝 - 铜表面的存在下，通过等离子体氧灰化除去抗蚀剂蚀刻掩模。进行铝 - 铜冶金在约400〜550℃的温度下的快速热退火。冲洗所得到的表面以除去残留的抗蚀剂材料。结果是无孔的铝铜冶金表面。

2. 发明授权

US5252515A Method for field inversion free multiple layer metallurgy VLSI processing 失效
标题翻译：无反向多层冶金超大规模集成电路处理方法
公开(公告)号：US5252515A
公开(公告)日：1993-10-12
申请号：US743779
申请日：1991-08-12
申请人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
发明人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
IPC分类号： H01L21/285 , H01L21/768 , H01L21/441 , H01L21/469
CPC分类号： H01L21/76834 , H01L21/28512 , H01L21/76819 , H01L21/76828 , H01L21/76832 , H01L2924/0002 , Y10S438/958
摘要： A multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.
摘要翻译：一种多层冶金，旋涂玻璃多层冶金结构和方法，用于在具有其中的器件区域图案的半导体衬底上具有基本自由场反转的1微米或更小的特征尺寸集成电路的这种结构。钝化层位于图案的表面上方。通过钝化层将至少一些包含源极/漏极区域的器件区域的开口图案制成。图案化的第一冶金层与开口图案接触。第一通孔介电层位于第一冶金层的图案之上。富硅屏障介电层位于第一层之上。固化的旋涂玻璃层在阻挡层上。氧化硅第二通孔电介质层在旋涂玻璃层上方。开口的图案在第二通孔层，旋涂玻璃层，阻挡层和第一通孔层中。图案化的第二冶金层与开口图案接触以与第一冶金层电接触，其中完成了具有基本自由场反转的多级冶金集成电路。

3. 发明授权

US5461254A Method and resulting device for field inversion free multiple layer metallurgy VLSI processing 失效
标题翻译：用于场反演自由多层冶金VLSI处理的方法和结果装置
公开(公告)号：US5461254A
公开(公告)日：1995-10-24
申请号：US350582
申请日：1994-12-06
申请人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
发明人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
IPC分类号： H01L21/285 , H01L21/768 , H01L23/58
CPC分类号： H01L21/76834 , H01L21/28512 , H01L21/76819 , H01L21/76828 , H01L21/76832 , H01L2924/0002 , Y10S438/958
摘要： There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.
摘要翻译：描述了一种多层冶金，旋涂玻璃多层冶金结构和方法，用于在具有其中的器件区域图案的半导体衬底上制造具有基本自由场反转的1微米或更小的特征尺寸集成电路的这种结构。钝化层位于图案的表面上方。通过钝化层将至少一些包含源极/漏极区域的器件区域的开口图案制成。图案化的第一冶金层与开口图案接触。第一通孔介电层位于第一冶金层的图案之上。富硅屏障介电层位于第一层之上。固化的旋涂玻璃层在阻挡层上。氧化硅第二通孔电介质层在旋涂玻璃层上方。开口的图案在第二通孔层，旋涂玻璃层，阻挡层和第一通孔层中。图案化的第二冶金层与开口图案接触以与第一冶金层电接触，其中完成了具有基本自由场反转的多级冶金集成电路。

4. 发明授权

US5286667A Modified and robust self-aligning contact process 失效
标题翻译：改进和鲁棒的自对准接触过程
公开(公告)号：US5286667A
公开(公告)日：1994-02-15
申请号：US925453
申请日：1992-08-11
申请人： Jiunn-Jyi Lin , Lih-Shyng Tsai , Hsien-Wen Chang , Chang-Tai Chiao
发明人： Jiunn-Jyi Lin , Lih-Shyng Tsai , Hsien-Wen Chang , Chang-Tai Chiao
IPC分类号： H01L21/02 , H01L21/60 , H01L21/762 , H01L27/06 , H01L27/092 , H01L21/82
CPC分类号： H01L21/76897 , H01L21/76202 , H01L27/0629 , H01L27/0925 , H01L28/40
摘要： The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silicon oxynitride barrier layers. The barrier layer is a key to the successful lightly doped drain spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.
摘要翻译：描述了用于制造具有栅电极和源/漏区的电容器和金属氧化物半导体场效应晶体管的组合的集成电路的方法。该方法的特征在于使用氮化硅或氮氧化硅阻挡层。阻挡层是成功的轻掺杂漏极间隔物蚀刻工艺的关键。阻挡层有助于等离子体蚀刻的端点检测。这允许场氧化物的较少损失和场氧化物区域的较大厚度控制。此外，氮化硅终点检测允许从电容器板的表面去除不期望的剩余氧化硅，而不会损失多晶硅电容器板本身。

5. 发明授权

US5334554A Nitrogen plasma treatment to prevent field device leakage in VLSI processing 失效
标题翻译：氮等离子体处理，以防止VLSI处理中的现场设备泄漏
公开(公告)号：US5334554A
公开(公告)日：1994-08-02
申请号：US825371
申请日：1992-01-24
申请人： Kwang-Ming Lin , Lih-Shyig Tsai , Jiunn-Jyi Lin , Yung-Haw Liaw
发明人： Kwang-Ming Lin , Lih-Shyig Tsai , Jiunn-Jyi Lin , Yung-Haw Liaw
IPC分类号： H01L21/768 , H01L21/469
CPC分类号： H01L21/76801 , H01L21/76819 , H01L21/76826 , H01L21/76828
摘要： A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns. Then the multilayer metallurgy is formed thereover by opening a pattern of openings through the passivation layer to at least some of the source/drain regions, depositing and patterning a first metallurgy layer in contact with the pattern of openings, forming a first via dielectric layer over the pattern of first metallurgy layer, exposing the first silicon oxide via dielectric layer to a nitrogen plasma, forming a spin-on-glass layer over the via dielectric layer and curing the layer, forming a second via dielectric layer over the spin-on-glass layer, forming a pattern of openings in the second via layer, the spin-on-glass layer, and the first via layer, and depositing and patterning a second metallurgy layer through the openings to make electrical contact with the first metallurgy layer.
摘要翻译：描述了一种用于形成具有基本自由场反转的一微米或更小特征尺寸集成电路的多层冶金，旋涂玻璃多层冶金的方法，即第一通孔层和SOG之间的正电荷。一种具有场效应器件源极/漏极区域的图案的半导体衬底，其栅极电介质和栅极电极结构的图案与其相关联，并且至少部分地在半导体衬底内的场隔离结构的图案将这些源极/漏极区域中的某些从提供了另一个。在所述图案的表面上形成钝化层。然后通过将通过钝化层的开口图案打开到至少一些源极/漏极区域，沉积和图案化与开口图案接触的第一冶金层，从而形成多层冶金，形成第一通孔电介质层所述第一冶金层的图案，通过介电层将所述第一氧化硅暴露于氮等离子体，在所述通孔电介质层上形成旋涂玻璃层并固化所述层，在所述自旋 - 玻璃层，在第二通孔层，旋涂玻璃层和第一通孔层中形成开口图案，并且通过开口沉积和图案化第二冶金层以与第一冶金层电接触。

6. 发明授权

US5629237A Taper etching without re-entrance profile 失效
标题翻译：锥形蚀刻无需重新进入型材
公开(公告)号：US5629237A
公开(公告)日：1997-05-13
申请号：US545380
申请日：1995-10-19
申请人： Pei-Jan Wang , Kuei-Lung Chou , Jiunn-Jyi Lin , Hsien-Wen Chang
发明人： Pei-Jan Wang , Kuei-Lung Chou , Jiunn-Jyi Lin , Hsien-Wen Chang
IPC分类号： H01L21/768 , H01L21/311
CPC分类号： H01L21/76804 , Y10S438/978
摘要： A method is described for forming tapered contact via holes in large scale integrated circuit structures which avoids the formation of a re-entrance profile. The re-entrance profile can form at the entrance to the contact via hole when a dry etch is used as a first etching step by redepositing material removed during the dry etch at the entrance of the contact via hole. This re-entrance profile makes the angle of entrance into the contact via hole greater than 90.degree. and the step coverage of metal filling the hole poor. This invention uses wet etching with a greater lateral etch rate than vertical etch rate as a first etching step in the formation of the contact via hole and avoids the formation of the re-entrance profile. The edges of the resulting contact via hole are smooth and the entrance angle into the contact via hole is substantially less than 90.degree.. The step coverage of metal later filling the contact via hole is substantially improved.
摘要翻译：描述了一种用于在大规模集成电路结构中形成锥形接触通孔的方法，其避免形成再入口轮廓。当使用干蚀刻作为第一蚀刻步骤时，通过在干蚀刻中去除的材料在接触通孔的入口处重新沉积材料，可以在接触孔的入口处形成再入口轮廓。这种再入口轮廓使接触孔的入口角大于90°，填充孔的金属台阶覆盖差。本发明使用具有比垂直蚀刻速率更大的横向蚀刻速率的湿蚀刻作为形成接触通孔的第一蚀刻步骤，并避免形成再入口轮廓。所得接触通孔的边缘是光滑的，并且接触通孔中的入射角基本上小于90°。稍后填充接触通孔的金属的台阶覆盖率显着提高。

7. 发明授权

US06844626B2 Bond pad scheme for Cu process 有权
公开(公告)号：US06844626B2
公开(公告)日：2005-01-18
申请号：US10444229
申请日：2003-05-23
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

8. 发明授权

US07015129B2 Bond pad scheme for Cu process 失效
标题翻译： Cu工艺的焊盘方案
公开(公告)号：US07015129B2
公开(公告)日：2006-03-21
申请号：US10999464
申请日：2004-11-29
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
摘要翻译：一种形成半导体器件的接合焊盘和新的接合焊盘结构的新颖方法。两个钝化层用于形成半导体器件的接合焊盘。第二钝化层的一部分位于相邻的接合焊盘之间，防止在随后的引线接合过程或倒装芯片封装工艺期间接合焊盘短路。

9. 发明申请

US20050095836A1 Bond pad scheme for Cu process 失效
标题翻译： Cu工艺的焊盘方案
公开(公告)号：US20050095836A1
公开(公告)日：2005-05-05
申请号：US10999464
申请日：2004-11-29
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
摘要翻译：一种形成半导体器件的接合焊盘和新的接合焊盘结构的新颖方法。两个钝化层用于形成半导体器件的接合焊盘。第二钝化层的一部分位于相邻的接合焊盘之间，防止在随后的引线接合过程或倒装芯片封装工艺期间接合焊盘短路。

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