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1. 发明授权

US5252515A Method for field inversion free multiple layer metallurgy VLSI processing 失效
标题翻译：无反向多层冶金超大规模集成电路处理方法
公开(公告)号：US5252515A
公开(公告)日：1993-10-12
申请号：US743779
申请日：1991-08-12
申请人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
发明人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
IPC分类号： H01L21/285 , H01L21/768 , H01L21/441 , H01L21/469
CPC分类号： H01L21/76834 , H01L21/28512 , H01L21/76819 , H01L21/76828 , H01L21/76832 , H01L2924/0002 , Y10S438/958
摘要： A multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.
摘要翻译：一种多层冶金，旋涂玻璃多层冶金结构和方法，用于在具有其中的器件区域图案的半导体衬底上具有基本自由场反转的1微米或更小的特征尺寸集成电路的这种结构。钝化层位于图案的表面上方。通过钝化层将至少一些包含源极/漏极区域的器件区域的开口图案制成。图案化的第一冶金层与开口图案接触。第一通孔介电层位于第一冶金层的图案之上。富硅屏障介电层位于第一层之上。固化的旋涂玻璃层在阻挡层上。氧化硅第二通孔电介质层在旋涂玻璃层上方。开口的图案在第二通孔层，旋涂玻璃层，阻挡层和第一通孔层中。图案化的第二冶金层与开口图案接触以与第一冶金层电接触，其中完成了具有基本自由场反转的多级冶金集成电路。

2. 发明授权

US5461254A Method and resulting device for field inversion free multiple layer metallurgy VLSI processing 失效
标题翻译：用于场反演自由多层冶金VLSI处理的方法和结果装置
公开(公告)号：US5461254A
公开(公告)日：1995-10-24
申请号：US350582
申请日：1994-12-06
申请人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
发明人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
IPC分类号： H01L21/285 , H01L21/768 , H01L23/58
CPC分类号： H01L21/76834 , H01L21/28512 , H01L21/76819 , H01L21/76828 , H01L21/76832 , H01L2924/0002 , Y10S438/958
摘要： There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.
摘要翻译：描述了一种多层冶金，旋涂玻璃多层冶金结构和方法，用于在具有其中的器件区域图案的半导体衬底上制造具有基本自由场反转的1微米或更小的特征尺寸集成电路的这种结构。钝化层位于图案的表面上方。通过钝化层将至少一些包含源极/漏极区域的器件区域的开口图案制成。图案化的第一冶金层与开口图案接触。第一通孔介电层位于第一冶金层的图案之上。富硅屏障介电层位于第一层之上。固化的旋涂玻璃层在阻挡层上。氧化硅第二通孔电介质层在旋涂玻璃层上方。开口的图案在第二通孔层，旋涂玻璃层，阻挡层和第一通孔层中。图案化的第二冶金层与开口图案接触以与第一冶金层电接触，其中完成了具有基本自由场反转的多级冶金集成电路。

3. 发明授权

US5248384A Rapid thermal treatment to eliminate metal void formation in VLSI manufacturing process 失效
标题翻译：快速热处理以消除VLSI制造过程中的金属空隙形成
公开(公告)号：US5248384A
公开(公告)日：1993-09-28
申请号：US803518
申请日：1991-12-09
申请人： Kwang-Ming Lin , Lih-Shyng Tsai , Jiunn-Jyi Lin , Chin-Twan Wei
发明人： Kwang-Ming Lin , Lih-Shyng Tsai , Jiunn-Jyi Lin , Chin-Twan Wei
IPC分类号： H01L21/321
CPC分类号： H01L21/321
摘要： The method of forming a void-free surface on aluminum-copper metallurgy after stripping of resist is described. There is provided an aluminum-copper metallurgy on a suitable substrate, such as a semiconductor integrated circuit wafer during manufacture. A resist layer is formed over surface. The resist layer is exposing, developing and the developed resist is used as an etch mask to etch a layer, such as an insulating layer on the metallurgy which results in exposing the aluminum-copper metallurgy surface. The resist etch mask is removed by plasma oxygen ashing in presence of the exposed aluminum-copper surface. Rapid thermal annealing of the aluminum-copper metallurgy at a temperature of between about 400.degree. to 550.degree. C. is performed. The resulting surfaces are rinsed to remove any residual resist material. The result is a void-free aluminum-copper metallurgy surface.
摘要翻译：描述了剥离抗蚀剂后在铝 - 铜冶金学上形成无空隙表面的方法。在合适的基板上提供铝 - 铜冶金，例如在制造期间的半导体集成电路晶片。在表面上形成抗蚀剂层。抗蚀剂层是曝光，显影，并且显影的抗蚀剂用作蚀刻掩模以蚀刻诸如在冶金学上的绝缘层的层，这导致暴露铝 - 铜冶金表面。在暴露的铝 - 铜表面的存在下，通过等离子体氧灰化除去抗蚀剂蚀刻掩模。进行铝 - 铜冶金在约400〜550℃的温度下的快速热退火。冲洗所得到的表面以除去残留的抗蚀剂材料。结果是无孔的铝铜冶金表面。

4. 发明授权

US5286667A Modified and robust self-aligning contact process 失效
标题翻译：改进和鲁棒的自对准接触过程
公开(公告)号：US5286667A
公开(公告)日：1994-02-15
申请号：US925453
申请日：1992-08-11
申请人： Jiunn-Jyi Lin , Lih-Shyng Tsai , Hsien-Wen Chang , Chang-Tai Chiao
发明人： Jiunn-Jyi Lin , Lih-Shyng Tsai , Hsien-Wen Chang , Chang-Tai Chiao
IPC分类号： H01L21/02 , H01L21/60 , H01L21/762 , H01L27/06 , H01L27/092 , H01L21/82
CPC分类号： H01L21/76897 , H01L21/76202 , H01L27/0629 , H01L27/0925 , H01L28/40
摘要： The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silicon oxynitride barrier layers. The barrier layer is a key to the successful lightly doped drain spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.
摘要翻译：描述了用于制造具有栅电极和源/漏区的电容器和金属氧化物半导体场效应晶体管的组合的集成电路的方法。该方法的特征在于使用氮化硅或氮氧化硅阻挡层。阻挡层是成功的轻掺杂漏极间隔物蚀刻工艺的关键。阻挡层有助于等离子体蚀刻的端点检测。这允许场氧化物的较少损失和场氧化物区域的较大厚度控制。此外，氮化硅终点检测允许从电容器板的表面去除不期望的剩余氧化硅，而不会损失多晶硅电容器板本身。

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