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1. 发明授权

US06198121B1 Method fabricating a DRAM cell with an area equal to four times the used minimum feature 失效
标题翻译：制造具有等于使用的最小特征的四倍的面积的DRAM单元的方法
公开(公告)号：US06198121B1
公开(公告)日：2001-03-06
申请号：US09022405
申请日：1998-02-12
申请人： JanMye Sung
发明人： JanMye Sung
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： A DRAM cell structure, and a fabrication process to create the DRAM cell structure, has been developed. The area consumed by the DRAM cell structure is reduced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to an overlying capacitor structure. The process features creating a narrow hole in a polysilicon word line structure, and in overlying and underlying insulator layers. The narrow hole, when filled with single crystalline silicon, connects the polysilicon word line structure to an underlying bit line structure, as well as connecting to an overlying capacitor structure.
摘要翻译：已经开发了DRAM单元结构和用于创建DRAM单元结构的制造工艺。 DRAM单元结构消耗的面积通过垂直排列多晶硅字线结构，下层位线结构以及覆盖电容器结构来减少。该过程的特征是在多晶硅字线结构中以及在上层和下面的绝缘体层中产生窄孔。当填充单晶硅时，窄孔将多晶硅字线结构连接到下面的位线结构，以及连接到上覆电容器结构。

2. 发明授权

US5858831A Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip 失效
标题翻译：在单个半导体芯片上制造高性能逻辑和嵌入式显示器件的工艺
公开(公告)号：US5858831A
公开(公告)日：1999-01-12
申请号：US31683
申请日：1998-02-27
申请人： Janmye Sung
发明人： Janmye Sung
IPC分类号： H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/105 , H01L21/20
CPC分类号： H01L27/10844 , H01L21/823871 , H01L27/105 , H01L27/1052 , H01L27/10873
摘要： A process for creating a region of high performance logic devices, and a region of low cost memory devices, on a single semiconductor chip, has been developed. The process features CMOS logic devices, comprised of polycide gate structures, residing on a thin silicon dioxide gate insulator layer. An N type polysilicon layer, used as part of a polycide structure, is used with the N channel CMOS devices, while a P type polysilicon layer, is used with the P channel CMOS devices. DRAM memory devices are comprised of polycide gate structures, featuring only an N type polysilicon layer, on a silicon dioxide gate insulator layer, that is thicker than the gate silicon oxide layer used with the high performance logic devices. A minimum of additional photolithographic masking procedures is used to improve the performance of the logic region, one mask to allow specific polycide gate structures to be created with either P type or N type polysilicon, and another additional mask used to allow different gate insulator layers to be formed in each specific region. A large angle, ion implantation procedure, is used to form lightly doped source and drain regions, under the silicon nitride spacers on the sides of polycide gate structures, in both logic and DRAM memory regions.
摘要翻译：已经开发了在单个半导体芯片上创建高性能逻辑器件区域和低成本存储器件的区域的工艺。该工艺具有驻留在薄的二氧化硅栅极绝缘体层上的由多晶硅栅极结构组成的CMOS逻辑器件。使用N型多晶硅层作为多晶硅结构的一部分，与N沟道CMOS器件一起使用，而P型多晶硅层与P沟道CMOS器件一起使用。 DRAM存储器件包括在二氧化硅栅绝缘层上仅具有N型多晶硅层的多晶硅栅极结构，其比与高性能逻辑器件一起使用的栅极氧化硅层厚。使用最小的附加光刻掩模程序来改善逻辑区域的性能，一个掩模允许用P型或N型多晶硅产生特定的多晶硅栅极结构，以及用于允许不同栅极绝缘体层在每个特定区域形成。使用大角度离子注入程序在逻辑和DRAM存储区域中在多晶硅栅极结构的侧面上的氮化硅间隔物下方形成轻掺杂的源极和漏极区域。

3. 发明授权

US5789291A Dram cell capacitor fabrication method 失效
标题翻译：电容器制造方法
公开(公告)号：US5789291A
公开(公告)日：1998-08-04
申请号：US512238
申请日：1995-08-07
申请人： Janmye Sung
发明人： Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A process for fabricating stacked capacitor, DRAM devices, wherein the surface area of the capacitor is significantly increased as a result of sidewall processes, has been developed. The process is highlighted by deposition of polysilicon, to be used for the lower electrode of the stacked capacitor structure, on specific underlying insulator shapes. As a result of the severe underlying insulator topography, a significant portion of the polysilicon forms on the sides of the underlying insulator shapes, creating a significant increase in the lower electrode surface area, which relates to marked increases in capacitance and device signal.
摘要翻译：已经开发了用于制造堆叠电容器，DRAM器件的方法，其中由于侧壁工艺，电容器的表面积显着增加。通过沉积用于层叠电容器结构的下电极的多晶硅，特定的下面的绝缘体形状来突出该过程。由于严重的下面的绝缘体形貌，大部分多晶硅在下面的绝缘体形状的侧面上形成，导致下部电极表面积的显着增加，这与电容和器件信号的显着增加有关。

4. 发明授权

US5679589A FET with gate spacer 失效
标题翻译： FET带栅极间隔
公开(公告)号：US5679589A
公开(公告)日：1997-10-21
申请号：US866942
申请日：1992-04-03
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
摘要翻译：公开了一种半导体集成电路结构及其制造方法。该结构包括具有相邻的双层或三层栅极间隔物的FET栅极。间隔物允许精细地定制具有深浅接合部分的轻掺杂漏极结型材。此外，自对准硅化物可以仅形成在深结部分上方，从而产生与源极和漏极的可靠的低接触电阻连接。

5. 发明授权

US5470783A Method for integrated circuit device isolation 失效
标题翻译：集成电路器件隔离方法
公开(公告)号：US5470783A
公开(公告)日：1995-11-28
申请号：US369977
申请日：1995-01-09
申请人： Tzu-Yin Chiu , Frank M. Erceg , Te-Yin M. Liu , Kenenth G. Moerschel , Michael A. Prozonic , Janmye Sung
发明人： Tzu-Yin Chiu , Frank M. Erceg , Te-Yin M. Liu , Kenenth G. Moerschel , Michael A. Prozonic , Janmye Sung
IPC分类号： H01L21/316 , H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76205 , H01L21/32 , Y10S148/05
摘要： An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls. The exposed portions of the second nitride layer are then removed, leaving only those portions of the second nitride layer that are interposed between the polycrystalline material and the sidewalls on the substrate surface. The remaining portions of the polycrystalline material on the surface of the structure are then removed. The field oxide is then grown on the field oxide region of the substrate. The portions of the second nitride layer on the sidewalls are lifted and bent as the oxide is grown. The lifting and bending of the second nitride layer forms grooves in the field oxide as it is grown. The remaining layers of the mask are then removed. A thin layer of oxide is then grown or deposited on the surface of the substrate. A layer of nitride with a thickness that is at least one-half the width of the grooves in the field oxide is deposited on the substrate surface. The nitride layer is then removed except for that portion of the nitride in the grooves.
摘要翻译：公开了一种用于在衬底中产生场氧化物区域的集成电路制造工艺。在该过程中，在衬底上形成氧化物，氮化物和沉积的二氧化硅的掩蔽层。通过这些掩模层将限定衬底中的场氧化物区域的图案引入到衬底中。场氧化物区域由衬底的一部分中的陡峭的侧壁和覆盖衬底的掩模层所界定。在衬底的暴露部分上生长薄层的氧化物，并且在衬底/掩模结构之上形成保形第二氮化层，随后是多晶材料的共形层。选择性地去除多晶层，使得保留在结构上的多晶材料的唯一部分是覆盖侧壁的部分。然后去除第二氮化物层的暴露部分，仅留下介于多晶材料和衬底表面上的侧壁之间的第二氮化物层的那些部分。然后除去结构表面上的多晶材料的剩余部分。然后，场氧化物在衬底的场氧化物区域上生长。当氧化物生长时，侧壁上的第二氮化物层的部分被提升和弯曲。当第二氮化物层生长时，第二氮化物层的提升和弯曲在场氧化物中形成凹槽。然后去除掩模的剩余层。然后在衬底的表面上生长或沉积薄层氧化物。厚度为场氧化物中沟槽宽度的至少一半的氮化物层沉积在衬底表面上。然后去除氮化物层，除了沟槽中的那部分氮化物。

6. 发明授权

US6137130A Capacitor over bit line structure using a straight bit line shape 有权
标题翻译：使用直线形状的位线结构电容器
公开(公告)号：US6137130A
公开(公告)日：2000-10-24
申请号：US455357
申请日：1999-12-06
申请人： Janmye Sung
发明人： Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852
摘要： A method of creating a capacitor over bit line structure, used for high density, DRAM designs, has been developed. The process consists of creating a straight bit line shape, connected to an underlying polysilicon contact plug structure, which in turn contacts an underlying source and drain region. A storage node contact hole is opened through insulator layers and through the straight bit line shape. After passivation of the storage node contact hole with silicon nitride spacers, a storage node structure is formed on an overlying insulator layer, as well as in the storage node contact hole, overlying and contacting another polysilicon contact plug.
摘要翻译：已经开发了用于高密度DRAM设计的位线结构上产生电容器的方法。该过程包括产生直的位线形状，连接到下面的多晶硅接触插塞结构，其又接触下面的源极和漏极区域。存储节点接触孔通过绝缘体层和直的位线形状打开。在用氮化硅间隔物钝化存储节点接触孔之后，在覆盖的绝缘体层以及存储节点接触孔中形成存储节点结构，覆盖并接触另一个多晶硅接触插塞。

7. 发明授权

US6136643A Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology 有权
标题翻译：使用自对准接触蚀刻技术制造电容器 - 位线动态随机存取存储器（DRAM）的方法
公开(公告)号：US6136643A
公开(公告)日：2000-10-24
申请号：US248727
申请日：1999-02-11
申请人： Erik S. Jeng , Chun-Yao Chen , Ing-Ruey Liaw , Janmye Sung
发明人： Erik S. Jeng , Chun-Yao Chen , Ing-Ruey Liaw , Janmye Sung
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10888 , H01L28/91
摘要： A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electrodes in the openings, and the third oxide layer is removed, while the Si.sub.3 N.sub.4 etch-stop layers prevents over-etching. An interelectrode dielectric layer is deposited, and capacitor top electrodes are formed.
摘要翻译：实现了使用自对准接触蚀刻技术制造电容器对位线（COB）DRAM的方法。在形成FET栅电极之后，侧壁间隔物由第一Si 3 N 4蚀刻停止层形成，而一部分Si 3 N 4作为蚀刻停止层保留在源/漏区上。自对准的接触开口在第一氧化物层中蚀刻到源极/漏极区域，并且在所有自对准开口中形成多晶硅着色塞。沉积第二氧化物层，并将接触孔蚀刻到位线的着陆塞。沉积具有盖层的多晶硅化物层并构图以形成位线。第三个Si 3 N 4蚀刻停止层被保形地沉积在位线上并被图案化以在用于电容器节点接触的着陆塞上形成开口，同时在开口中暴露的位线上形成Si 3 N 4侧壁间隔物。沉积第三氧化物层，并且具有松弛的取向公差的开口可被蚀刻到电容器节点接点，因为下面的第三蚀刻停止层防止过蚀刻。导电层被沉积并回蚀刻以在开口中形成底部电极，并且去除第三氧化物层，而Si 3 N 4蚀刻停止层防止过蚀刻。沉积电极间电介质层，形成电容器顶部电极。

8. 发明授权

US5821142A Method for forming a capacitor with a multiple pillar structure 失效
标题翻译：一种形成具有多支柱结构的电容器的方法
公开(公告)号：US5821142A
公开(公告)日：1998-10-13
申请号：US629158
申请日：1996-04-08
申请人： JanMye Sung , Howard C. Kirsch , Chih-Yuan Lu
发明人： JanMye Sung , Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/92 , H01L28/84 , Y10S438/947 , Y10S438/968
摘要： The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.
摘要翻译：本发明提供一种制造多柱形电容器的方法，该多柱形电容器的尺寸小于光刻工具的分辨率。本发明具有用于形成支柱的两个实施例和用于将导电层图案化成离散底部电极的第三实施例。该方法开始于在第一平坦化层上形成导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔开的透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率的尺寸。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。第三实施例使用两个抗蚀剂层和光掩模移位（偏移）技术在电极之间形成小的空间。最后，在底部电极上形成电容器电介质层和顶部电极，由此完成具有柱状结构的电容器。

9. 发明授权

US5656510A Method for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current control 失效
标题翻译：制造栅极氧化物电容器的方法，包括晶片背面电介质和注入电子喷枪电流控制
公开(公告)号：US5656510A
公开(公告)日：1997-08-12
申请号：US344318
申请日：1994-11-22
申请人： Terry Chrapacz , Kenneth Gordon Moerschel , William A. Possanza , Michael Allen Prozonic , Janmye Sung
发明人： Terry Chrapacz , Kenneth Gordon Moerschel , William A. Possanza , Michael Allen Prozonic , Janmye Sung
IPC分类号： H01L21/265 , H01L21/28 , H01L21/318 , H01L21/322 , H01L23/60
CPC分类号： H01L23/60 , H01L21/28035 , H01L2924/0002 , Y10S438/928
摘要： A method is provided for optimizing the manufacturing yield of semiconductors. The method provides a backside dielectric layer which protects the semiconductor from electro-static discharge damage during manufacturing. The backside dielectric layer may be a nitride. The backside dielectric layer may be an oxide. The method also provides for optimized ion implantation flood gun current control.
摘要翻译：提供了一种优化半导体制造产量的方法。该方法提供了在制造期间保护半导体免受静电放电损坏的背面电介质层。背面电介质层可以是氮化物。背面电介质层可以是氧化物。该方法还提供优化的离子注入洪水枪电流控制。

10. 发明授权

US5547893A method for fabricating an embedded vertical bipolar transistor and a memory cell 失效
标题翻译：用于制造嵌入式垂直双极晶体管和存储单元的方法
公开(公告)号：US5547893A
公开(公告)日：1996-08-20
申请号：US578923
申请日：1995-12-27
申请人： JanMye Sung
发明人： JanMye Sung
IPC分类号： H01L21/8242 , H01L21/8249 , H01L27/06 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/8249 , H01L27/0623
摘要： The present invention provides a method of simultaneously forming CMOS DRAM cells, CMOS devices, and vertical bipolar transistors on the same chip. The invention utilities a CMOS DRAM process to simultaneously fabricate a vertical bipolar transistor and uses only one additional mask (a base implant mask) compared to forming the DRAM cell alone. Also, to reduce the bipolar collector plug resistance, the process uses a tungsten-plug module where the collector is formed within a field oxide region near the base.
摘要翻译：本发明提供了在同一芯片上同时形成CMOS DRAM单元，CMOS器件和垂直双极晶体管的方法。与仅形成DRAM单元相比，本发明实用于CMOS DRAM工艺以同时制造垂直双极晶体管并且仅使用一个附加掩模（基极注入掩模）。此外，为了降低双极集电极插塞电阻，该方法使用钨 - 塞模块，其中集电极形成在靠近基极的场氧化物区域内。

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