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1. 发明授权

US5610628A Driving device for a display panel and a driving method of the same 失效
公开(公告)号：US5610628A
公开(公告)日：1997-03-11
申请号：US447246
申请日：1995-05-22
申请人： Kunihiko Yamamoto , Kiyohisa Matsui , Yutaka Ishii , Norio Yasunishi , Toshihiro Nakamura , Hajime Washio , Koki Taniguchi
发明人： Kunihiko Yamamoto , Kiyohisa Matsui , Yutaka Ishii , Norio Yasunishi , Toshihiro Nakamura , Hajime Washio , Koki Taniguchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3625
摘要： A driving device for a display apparatus having excellent contrast and a high display quality without crosstalk and display irregularities, and a driving method for the same are provided. In the driving device, scanning signals and data signals having a plurality of periodical inactive portions in one frame are applied to respective display dots. In the inactive term, a fixed voltage is applied to each of the display dots. The signal applied to the display dot is divided into small terms by the inactive portions, resulting in more high frequency components in a voltage signal applied to the display dot. As a result, the frequency components of a driving signal applied to the display dot are averaged. Further, a complete orthogonal function having 2.sup.r base function series is used, and a desired display data is completely reproduced on the display apparatus by an arithmetic process assuming auxiliary data in accordance with the number of the scanning electrodes.

2. 发明授权

US5594466A Driving device for a display panel and a driving method of the same 失效
标题翻译：显示面板的驱动装置及其驱动方法
公开(公告)号：US5594466A
公开(公告)日：1997-01-14
申请号：US132651
申请日：1993-10-05
申请人： Kunihiko Yamamoto , Kiyohisa Matsui , Yutaka Ishii , Norio Yasunishi , Toshihiro Nakamura , Hajime Washio , Koki Taniguchi
发明人： Kunihiko Yamamoto , Kiyohisa Matsui , Yutaka Ishii , Norio Yasunishi , Toshihiro Nakamura , Hajime Washio , Koki Taniguchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3625
摘要： A driving device for a display apparatus having excellent contrast and a high display quality without crosstalk and display irregularities, and a driving method for the same are provided. In the driving device, scanning signals and data signals having a plurality of periodical inactive portions in one frame are applied to respective display dots. In the inactive term, a fixed voltage is applied to each of the display dots. The signal applied to the display dot is divided into small terms by the inactive portions, resulting in more high frequency components in a voltage signal applied to the display dot. As a result, the frequency components of a driving signal applied to the display dot are averaged. Further, a complete orthogonal function having 2.sup.r base function series is used, and a desired display data is completely reproduced on the display apparatus by an arithmetic process assuming auxiliary data in accordance with the number of the scanning electrodes.
摘要翻译：提供了具有优异的对比度和高显示质量而没有串扰和显示不规则的显示装置的驱动装置及其驱动方法。在驱动装置中，在一个帧中具有多个周期性非活动部分的扫描信号和数据信号被施加到各个显示点。在无效项中，对每个显示点施加固定电压。施加到显示点的信号被非活动部分分成小项，导致施加到显示点的电压信号中的更高频率分量。结果，施加到显示点的驱动信号的频率分量被平均。此外，使用具有2r基本功能系列的完整正交函数，并且通过假设根据扫描电极的数量的辅助数据的算术处理在显示装置上完全再现期望的显示数据。

3. 发明申请

US20130141668A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20130141668A1
公开(公告)日：2013-06-06
申请号：US13816583
申请日：2011-05-20
申请人： Hajime Washio , Shinsuke Yokonuma
发明人： Hajime Washio , Shinsuke Yokonuma
IPC分类号： G02F1/1335
CPC分类号： G02F1/1335 , G02F1/133512 , G02F1/133555 , G02F1/1347 , G02F2001/133374 , G02F2001/133567 , G02F2001/133601 , G02F2203/62 , G09G3/3406 , G09G3/36 , G09G2300/0456 , G09G2300/0857 , G09G2330/022
摘要： A display device with low power consumption having increased added value is provided.There are provided a memory liquid crystal panel (10), a backlight (20), and a PET sheet (30). The memory liquid crystal panel (10) includes a plurality of pixel circuit parts (11) each having a reflecting electrode (12), a transmission electrode (13), and a memory circuit (14A). On the surface of the PET sheet (30), print patterns (32A to 32D) are formed by ink. In a transmission display mode, a region in which the print patterns (32A to 32D) are printed in the PET sheet (30) suppresses transmission of backlight light (Ps) and a region in which the print patterns are not printed transmits the backlight light (Ps) without suppressing light. In such a manner, a sub image (Sp) is additionally displayed in a main image (Mp).
摘要翻译：提供了具有增加附加值的低功耗的显示装置。设置有记忆液晶面板（10），背光源（20）和PET片材（30）。存储液晶面板（10）具有多个具有反射电极（12），透射电极（13）和存储电路（14A）的像素电路部（11）。在PET片（30）的表面上，通过墨水形成印刷图案（32A〜32D）。在透射显示模式中，印刷在PET片材（30）中的印刷图案（32A至32D）的区域抑制背光源（Ps）的传输，并且印刷图案未被印刷的区域传输背光灯（Ps）而不抑制光。以这种方式，副图像（Sp）被附加地显示在主图像（Mp）中。

4. 发明授权

US08411027B2 Image display apparatus 有权
标题翻译：图像显示装置
公开(公告)号：US08411027B2
公开(公告)日：2013-04-02
申请号：US12654397
申请日：2009-12-18
申请人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
发明人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G02F1/1362 , G09G2300/0452 , G09G2310/0218 , G09G2310/0297 , G09G2310/08 , G09G2320/0209
摘要： A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.
摘要翻译：多个扫描信号线GLn被分成组，并且每组由三个扫描信号线GLnR，GLnG和GLnB组成，并且多个像素被划分成像素块，并且每个像素块由三个像素PR （n，m），PG（n，m）和PB（n，m）分别连接到扫描信号线GLnR，GLnG和GLnB。这些像素PR（n，m），PG（n，m）和PB（n，m）连接到公共数据信号线SLm。对于扫描信号线GLnR，GLnG，GLnB，扫描脉冲从移位寄存器SRnR，SRnG和SRnB顺序地输出到扫描信号线GLnR，GLnG和GLnB，并且将用于R，G和B的视频信号输出到数据信号通过时分驱动IC的行SLm。

5. 发明授权

US07688302B2 Shift register and display device using same 有权
公开(公告)号：US07688302B2
公开(公告)日：2010-03-30
申请号：US11543218
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

6. 发明授权

US07505022B2 Shift register and display device 有权
标题翻译：移位寄存器和显示设备
公开(公告)号：US07505022B2
公开(公告)日：2009-03-17
申请号：US11044003
申请日：2005-01-28
申请人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
发明人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G11C19/00 , G11C19/28
摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
摘要翻译：在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并产生从其重叠部分被去除的输出信号A（A1，A2 ...）。波形定时形成部输出通过提取在相应的相位差检测部中产生的输出信号A（A1，A2 ......）的高电平的期间而获得的输出信号X（X1，X2 ...），当来自相应触发器的输出信号Q（Q1，Q2 ...）为高。输出信号X（X1，X2，...）在下一阶段设置触发器。根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。也可以实现具有移位寄存器的显示装置。

7. 发明申请

US20090009374A1 DIGITAL TO ANALOGUE CONVERTER 失效
标题翻译：数字到模拟转换器
公开(公告)号：US20090009374A1
公开(公告)日：2009-01-08
申请号：US11793522
申请日：2006-01-11
申请人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
发明人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
IPC分类号： H03M1/66
CPC分类号： H03M1/802
摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.
摘要翻译：一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1））开关电容器; 和切换装置。在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入所述至少一个电容器。在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

8. 发明授权

US07414607B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07414607B2
公开(公告)日：2008-08-19
申请号：US10733395
申请日：2003-12-12
申请人： Hajime Washio , Kazuhiro Maeda , Mamoru Onda
发明人： Hajime Washio , Kazuhiro Maeda , Mamoru Onda
IPC分类号： G09G3/36 , G09G5/00 , G06F3/038
CPC分类号： G09G3/3688 , G09G3/3607 , G09G3/3677 , G09G2300/043 , G09G2310/0248 , G09G2320/0223 , G09G2330/021
摘要： In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCK1 and SCK2 are supplied to the first data signal line driving circuit SD1, while the first clock signal SCK1 is also supplied to the second data signal line driving circuit SD2 in parallel. The wirings 1 and 2 for the respective signals are adjusted to have equal wiring load with a dummy wiring 2 provided in the wiring 2, for solving uneven wiring load caused by difference of leading manner, the dummy wiring 2 constituting an additional capacitor section 7, together with a liquid crystal layer and a counter electrode.
摘要翻译：在将这些信号相互关联的多个信号提供给驱动电路的结构中，至少一个信号也被提供给另一个电路的结构中，本发明防止了多个信号之间的相位关系的变化由于接线负载不同，无需直接处理具有较高功耗的信号。第一和第二时钟信号SCK 1和SCK 2被提供给第一数据信号线驱动电路SD 1，而第一时钟信号SCK 1也被并行地提供给第二数据信号线驱动电路SD 2。对于各信号的布线1和2被调整为具有与配线2中设置的虚拟布线2相同的布线负载，用于解决由引导方式的差引起的不均匀布线负载，构成附加电容器部分7的虚拟布线2，与液晶层和对电极一起。

9. 发明申请

US20080158129A1 Display Device Driving Circuit and Display Device Including Same 有权
标题翻译：显示设备驱动电路和包括其的显示设备
公开(公告)号：US20080158129A1
公开(公告)日：2008-07-03
申请号：US11665206
申请日：2005-05-10
申请人： Yuhichiroh Murakami , Hajime Washio
发明人： Yuhichiroh Murakami , Hajime Washio
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0248
摘要： In an embodiment, a sampling signal to each data signal line is generated by using an output signal outputted from each flip-flop, and a precharge signal by which the data signal line to which the sampling signal is to be outputted is precharged is generated by using an output signal outputted from an output terminal of the flip-flop. Further, by providing a NOR circuit, an active period of the precharge signal and an active period of the sampling signal are prevented from overlapping each other. With this, in an embodiment of a display device driving circuit, including a precharge circuit, which causes a precharge power supply to precharge signal supply lines, the number of shift registers and the size of a circuit can be reduced.
摘要翻译：在一个实施例中，通过使用从每个触发器输出的输出信号和通过其将要输出采样信号的数据信号线预充电的预充电信号来产生对每个数据信号线的采样信号，该预充电信号由使用从触发器的输出端子输出的输出信号。此外，通过提供NOR电路，防止预充电信号的有效周期和采样信号的有效周期彼此重叠。由此，在包括预充电电路的预充电电路的显示装置驱动电路的实施例中，其使预充电电源对信号供给线进行预充电，可以减少移位寄存器的数量和电路的尺寸。

10. 发明申请

US20080036753A1 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US20080036753A1
公开(公告)日：2008-02-14
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW，不仅在第一帧中显示，而且在预定数量的帧中显示一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

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