专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08411027B2 Image display apparatus 有权
标题翻译：图像显示装置
公开(公告)号：US08411027B2
公开(公告)日：2013-04-02
申请号：US12654397
申请日：2009-12-18
申请人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
发明人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G02F1/1362 , G09G2300/0452 , G09G2310/0218 , G09G2310/0297 , G09G2310/08 , G09G2320/0209
摘要： A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.
摘要翻译：多个扫描信号线GLn被分成组，并且每组由三个扫描信号线GLnR，GLnG和GLnB组成，并且多个像素被划分成像素块，并且每个像素块由三个像素PR （n，m），PG（n，m）和PB（n，m）分别连接到扫描信号线GLnR，GLnG和GLnB。这些像素PR（n，m），PG（n，m）和PB（n，m）连接到公共数据信号线SLm。对于扫描信号线GLnR，GLnG，GLnB，扫描脉冲从移位寄存器SRnR，SRnG和SRnB顺序地输出到扫描信号线GLnR，GLnG和GLnB，并且将用于R，G和B的视频信号输出到数据信号通过时分驱动IC的行SLm。

2. 发明申请

US20050200591A1 Image display apparatus 有权
标题翻译：图像显示装置
公开(公告)号：US20050200591A1
公开(公告)日：2005-09-15
申请号：US11058301
申请日：2005-02-16
申请人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
发明人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3677 , G02F1/1362 , G09G2300/0452 , G09G2310/0218 , G09G2310/0297 , G09G2310/08 , G09G2320/0209
摘要： A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.
摘要翻译：多个扫描信号线GLn被分成组，并且每组由三个扫描信号线GLnR，GLnG和GLnB组成，并且多个像素被划分成像素块，并且每个像素块由三个像素PR （n，m），PG（n，m）和PB（n，m）分别连接到扫描信号线GLnR，GLnG和GLnB。这些像素PR（n，m），PG（n，m）和PB（n，m）连接到公共数据信号线SLm。对于扫描信号线GLnR，GLnG，GLnB，扫描脉冲从移位寄存器SRnR，SRnG和SRnB顺序地输出到扫描信号线GLnR，GLnG和GLnB，并且将用于R，G和B的视频信号输出到数据信号通过时分驱动IC的行SLm。

3. 发明授权

US07649521B2 Image display apparatus 有权
标题翻译：图像显示装置
公开(公告)号：US07649521B2
公开(公告)日：2010-01-19
申请号：US11058301
申请日：2005-02-16
申请人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
发明人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
IPC分类号： G09G3/36 , G09G5/00 , G06F3/038
CPC分类号： G09G3/3677 , G02F1/1362 , G09G2300/0452 , G09G2310/0218 , G09G2310/0297 , G09G2310/08 , G09G2320/0209
摘要： A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.
摘要翻译：多个扫描信号线GLn被分成组，并且每组由三个扫描信号线GLnR，GLnG和GLnB组成，并且多个像素被划分成像素块，并且每个像素块由三个像素PR （n，m），PG（n，m）和PB（n，m）分别连接到扫描信号线GLnR，GLnG和GLnB。这些像素PR（n，m），PG（n，m）和PB（n，m）连接到公共数据信号线SLm。对于扫描信号线GLnR，GLnG，GLnB，扫描脉冲从移位寄存器SRnR，SRnG和SRnB顺序地输出到扫描信号线GLnR，GLnG和GLnB，并且将用于R，G和B的视频信号输出到数据信号通过时分驱动IC的行SLm。

4. 发明申请

US20100103153A1 Image display apparatus 有权
公开(公告)号：US20100103153A1
公开(公告)日：2010-04-29
申请号：US12654397
申请日：2009-12-18
申请人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
发明人： Masakazu Satoh , Hajime Washio , Sadahiko Yasukawa
IPC分类号： G09G5/00 , H04N3/00
CPC分类号： G09G3/3677 , G02F1/1362 , G09G2300/0452 , G09G2310/0218 , G09G2310/0297 , G09G2310/08 , G09G2320/0209
摘要： A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.

5. 发明授权

US06724363B1 Two-way shift register and image display device using the same 有权
公开(公告)号：US06724363B1
公开(公告)日：2004-04-20
申请号：US09568889
申请日：2000-05-11
申请人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
发明人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G336
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G09G2310/0283 , G09G2310/0289 , G09G2330/021 , G11C19/28
摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.

6. 发明授权

US07365727B2 Two-way shift register and image display device using the same 失效
标题翻译：双向移位寄存器和图像显示装置使用相同
公开(公告)号：US07365727B2
公开(公告)日：2008-04-29
申请号：US10788161
申请日：2004-02-25
申请人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
发明人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G09G2310/0283 , G09G2310/0289 , G09G2330/021 , G11C19/28
摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.
摘要翻译：移位寄存器具有移位寄存器部分，该移位寄存器部分由与时钟信号同步操作的多级触发器组成;以及电平移位器，用于升压低于驱动电压的启动信号，并将其施加到两端的移位寄存器，并且移位寄存器能够根据切换信号切换移位方向。上述电平移位器是电流驱动型电平移位器，即使在晶体管特性较差的情况下或者在快速操作的情况下也能够工作，并且即使利用具有小振幅的启动信号也能进行电平移位。此外，上述电平移位器分别设置在移位寄存器部分的两端，并且其中一个电平移位器根据切换信号停止工作，从而消耗的功率应该减小。因此，可以提供能够在两个方向上移位的移位寄存器，即使在具有小幅度的输入信号的情况下也能正常地进行操作，因此消耗较少的电力。

7. 发明申请

US20130141668A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20130141668A1
公开(公告)日：2013-06-06
申请号：US13816583
申请日：2011-05-20
申请人： Hajime Washio , Shinsuke Yokonuma
发明人： Hajime Washio , Shinsuke Yokonuma
IPC分类号： G02F1/1335
CPC分类号： G02F1/1335 , G02F1/133512 , G02F1/133555 , G02F1/1347 , G02F2001/133374 , G02F2001/133567 , G02F2001/133601 , G02F2203/62 , G09G3/3406 , G09G3/36 , G09G2300/0456 , G09G2300/0857 , G09G2330/022
摘要： A display device with low power consumption having increased added value is provided.There are provided a memory liquid crystal panel (10), a backlight (20), and a PET sheet (30). The memory liquid crystal panel (10) includes a plurality of pixel circuit parts (11) each having a reflecting electrode (12), a transmission electrode (13), and a memory circuit (14A). On the surface of the PET sheet (30), print patterns (32A to 32D) are formed by ink. In a transmission display mode, a region in which the print patterns (32A to 32D) are printed in the PET sheet (30) suppresses transmission of backlight light (Ps) and a region in which the print patterns are not printed transmits the backlight light (Ps) without suppressing light. In such a manner, a sub image (Sp) is additionally displayed in a main image (Mp).
摘要翻译：提供了具有增加附加值的低功耗的显示装置。设置有记忆液晶面板（10），背光源（20）和PET片材（30）。存储液晶面板（10）具有多个具有反射电极（12），透射电极（13）和存储电路（14A）的像素电路部（11）。在PET片（30）的表面上，通过墨水形成印刷图案（32A〜32D）。在透射显示模式中，印刷在PET片材（30）中的印刷图案（32A至32D）的区域抑制背光源（Ps）的传输，并且印刷图案未被印刷的区域传输背光灯（Ps）而不抑制光。以这种方式，副图像（Sp）被附加地显示在主图像（Mp）中。

8. 发明授权

US07688302B2 Shift register and display device using same 有权
公开(公告)号：US07688302B2
公开(公告)日：2010-03-30
申请号：US11543218
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

9. 发明授权

US07505022B2 Shift register and display device 有权
标题翻译：移位寄存器和显示设备
公开(公告)号：US07505022B2
公开(公告)日：2009-03-17
申请号：US11044003
申请日：2005-01-28
申请人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
发明人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G11C19/00 , G11C19/28
摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
摘要翻译：在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并产生从其重叠部分被去除的输出信号A（A1，A2 ...）。波形定时形成部输出通过提取在相应的相位差检测部中产生的输出信号A（A1，A2 ......）的高电平的期间而获得的输出信号X（X1，X2 ...），当来自相应触发器的输出信号Q（Q1，Q2 ...）为高。输出信号X（X1，X2，...）在下一阶段设置触发器。根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。也可以实现具有移位寄存器的显示装置。

10. 发明申请

US20090009374A1 DIGITAL TO ANALOGUE CONVERTER 失效
标题翻译：数字到模拟转换器
公开(公告)号：US20090009374A1
公开(公告)日：2009-01-08
申请号：US11793522
申请日：2006-01-11
申请人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
发明人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
IPC分类号： H03M1/66
CPC分类号： H03M1/802
摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.
摘要翻译：一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1））开关电容器; 和切换装置。在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入所述至少一个电容器。在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式