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1. 发明申请

US20050186722A1 Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions 审中-公开
标题翻译：具有通过离子注入碳或含氧离子松弛应力的CMOS器件的方法和结构
公开(公告)号：US20050186722A1
公开(公告)日：2005-08-25
申请号：US10786643
申请日：2004-02-25
申请人： Kuan-Lun Cheng , Huan-Tsung Huang , Shui-Ming Cheng , Yin-Pin Wang , Ka-Hing Fung
发明人： Kuan-Lun Cheng , Huan-Tsung Huang , Shui-Ming Cheng , Yin-Pin Wang , Ka-Hing Fung
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/31155 , H01L21/76825 , H01L21/76829 , H01L21/823807 , H01L21/823828 , H01L21/823871 , H01L29/7842 , H01L29/7843
摘要： Stress in a silicon nitride contact etch stop layer on a CMOS structure having NMOS and PMOS devices is selectively relieved by selective implantation of oxygen-containing or carbon-containing ions resulting in there being no tensile stress in areas of the layer above the PMOS devices and no compressive stress in areas of the layer above the NMOS devices.
摘要翻译：在具有NMOS和PMOS器件的CMOS结构上的氮化硅接触蚀刻停止层中的应力通过选择性注入含氧或含碳离子来选择性地释放，导致在PMOS器件上方的层的区域中不存在拉伸应力，在NMOS器件上方的层的区域中没有压应力。

2. 发明授权

US06960512B2 Method for manufacturing a semiconductor device having an improved disposable spacer 失效
标题翻译：一种具有改进的一次性间隔件的半导体器件的制造方法
公开(公告)号：US06960512B2
公开(公告)日：2005-11-01
申请号：US10602241
申请日：2003-06-24
申请人： Shui-Ming Cheng , Ka-Hing Fung , Yin-Pin Wang , Kuan-Lun Cheng , Huan-Tsung Huang
发明人： Shui-Ming Cheng , Ka-Hing Fung , Yin-Pin Wang , Kuan-Lun Cheng , Huan-Tsung Huang
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide. The method also includes implanting impurities into the substrate using the gate electrode as an implant mask to form lightly-doped regions in the substrate. The method further includes forming a first spacer adjacent the gate electrode, and implanting impurities into the substrate and through a portion of the lightly-doped regions using the first spacer as an implant mask to form deep source/drain regions in the substrate. The method still further includes forming a second spacer adjacent the first spacer, implanting impurities into the substrate using the second spacer as an implant mask to form a graded source/drain region in the substrate, and removing the second spacer. Also disclosed is a semiconductor device constructed using the techniques disclosed herein.
摘要翻译：本发明提供半导体器件的制造方法。在一个实施例中，该方法包括在衬底上形成栅极氧化物，并在栅极氧化物上形成栅电极。该方法还包括使用栅电极作为注入掩模将杂质植入到衬底中，以在衬底中形成轻掺杂区域。该方法还包括形成与栅电极相邻的第一间隔物，以及使用第一间隔物作为注入掩模将杂质注入衬底并通过一部分轻掺杂区域，以在衬底中形成深源/漏区。该方法还包括形成与第一间隔物相邻的第二间隔物，使用第二间隔物作为注入掩模将杂质注入到衬底中，以在衬底中形成渐变源极/漏极区域，以及去除第二间隔物。还公开了使用本文公开的技术构造的半导体器件。

3. 发明申请

US20050026342A1 Semiconductor device having improved short channel effects, and method of forming thereof 审中-公开
标题翻译：具有改善的短通道效应的半导体器件及其形成方法
公开(公告)号：US20050026342A1
公开(公告)日：2005-02-03
申请号：US10628747
申请日：2003-07-28
申请人： Ka-Hing Fung , Yin-Ping Wang , Huan-Tsung Huang
发明人： Ka-Hing Fung , Yin-Ping Wang , Huan-Tsung Huang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/6653 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/66575 , H01L29/66772
摘要： Semiconductor device having improved short channel effects and method of forming thereof. One method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide, and implanting impurities into the substrate using the gate electrode as an implant mask to form a lightly-doped region in the substrate. The method includes depositing second spacer material adjacent to the gate electrode, forming a first spacer on the second spacer material, and implanting impurities into the substrate and through a portion of the lightly-doped region using the first spacer as an implant mask to form a first junction region in the substrate. The method includes removing the first spacer, etching the second spacer material to form a second spacer adjacent the gate electrode, and implanting impurities into the substrate using the second spacer as an implant mask to form a second junction region in the substrate.
摘要翻译：具有改善的短通道效应的半导体器件及其形成方法。一种方法包括在栅极氧化物上方形成衬底上的栅极氧化物和栅电极，以及使用栅电极作为注入掩模将杂质注入到衬底中，以在衬底中形成轻掺杂区域。该方法包括沉积与栅电极相邻的第二间隔物材料，在第二间隔物材料上形成第一间隔物，以及通过使用第一间隔物作为植入物掩模将杂质注入基底并通过一部分轻掺杂区域形成衬底中的第一结区域。该方法包括去除第一间隔物，蚀刻第二间隔物材料以形成邻近栅电极的第二间隔物，以及使用第二间隔物作为注入掩模将杂质注入基底，以在基底中形成第二连接区域。

4. 发明申请

US20050260776A1 Structure and method for extraction of parasitic junction capacitance in deep submicron technology 审中-公开
标题翻译：深亚微米技术中寄生结电容的提取结构与方法
公开(公告)号：US20050260776A1
公开(公告)日：2005-11-24
申请号：US10848887
申请日：2004-05-19
申请人： Yin-Pin Wang , Huan-Tsung Huang
发明人： Yin-Pin Wang , Huan-Tsung Huang
IPC分类号： H01L21/336 , H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/02 , H01L27/06 , H01L27/12
CPC分类号： H01L22/34 , H01L27/0207 , H01L27/0605 , H01L27/0705 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a structure and method for determining a parasitic junction voltage that cannot be directly measured because of lack of space for a probe. For example, the method may be used with a test structure having at least two transistors pairs. The first transistor pair may include a shared source or drain associated with a parasitic junction capacitance (Csb1), and two gates spaced to enable direct measurement of Csb1. The second transistor pair may include a shared source or drain associated with a parasitic junction capacitance (Csb2), and two gates spaced to prevent direct measurement of Csb2. The method may involve measuring a first total junction capacitance (C1) of the first transistor pair, measuring Csb1, measuring a second total junction capacitance (C2) of the second transistor pair, and determining Csb2 using C1, C2, and Csb1.
摘要翻译：本公开提供了一种用于确定由于缺乏探针空间而不能直接测量的寄生结电压的结构和方法。例如，该方法可以与具有至少两个晶体管对的测试结构一起使用。第一晶体管对可以包括与寄生结电容（Csb 1）相关联的共享源极或漏极，并且两个门间隔开以实现Csb 1的直接测量。第二晶体管对可以包括与寄生结电容（Csb 2）相关联的共享源极或漏极，以及间隔开的两个门，以防止直接测量Csb 2。该方法可以包括测量第一晶体管对的第一总结电容（C 1），测量Csb 1，测量第二晶体管对的第二总结电容（C 2），并使用C 1，C 2确定Csb 2 ，和Csb 1。

5. 发明授权

US08415749B2 Semiconductor structure with dielectric-sealed doped region 有权
公开(公告)号：US08415749B2
公开(公告)日：2013-04-09
申请号：US11788226
申请日：2007-04-19
申请人： Huan-Tsung Huang , Kou-Cheng Wu , Carlos H. Diaz
发明人： Huan-Tsung Huang , Kou-Cheng Wu , Carlos H. Diaz
IPC分类号： H01L29/51
CPC分类号： H01L21/76232 , H01L29/0653 , H01L29/66636 , H01L29/66651
摘要： Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

6. 发明申请

US20070284618A1 Transistor layout for standard cell with optimized mechanical stress effect 有权
标题翻译：具有优化机械应力效应的标准电池的晶体管布局
公开(公告)号：US20070284618A1
公开(公告)日：2007-12-13
申请号：US11441557
申请日：2006-05-26
申请人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
发明人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
IPC分类号： H01L27/10 , H01L29/739
CPC分类号： H01L27/0207 , H01L27/11803 , H01L29/7849
摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.
摘要翻译：公开了一种用于标准单元中晶体管的布局。晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于该晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为非矩形。

7. 发明授权

US08324090B2 Method to improve dielectric quality in high-k metal gate technology 有权
标题翻译：提高高k金属栅极技术介质质量的方法
公开(公告)号：US08324090B2
公开(公告)日：2012-12-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
IPC分类号： H01L21/4763 , H01L25/11 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

8. 发明授权

US07759210B2 Method for forming a MOS device with reduced transient enhanced diffusion 失效
标题翻译：用于形成具有减小的瞬时增强扩散的MOS器件的方法
公开(公告)号：US07759210B2
公开(公告)日：2010-07-20
申请号：US11644077
申请日：2006-12-21
申请人： Huan-Tsung Huang , Fung Ka Hing
发明人： Huan-Tsung Huang , Fung Ka Hing
IPC分类号： H01L21/336
CPC分类号： H01L29/1083 , H01L21/26513 , H01L21/324 , H01L29/6659
摘要： A method for forming a MOS device on a semiconductor substrate includes steps of: forming a gate structure on the semiconductor substrate; implanting ions into the semiconductor substrate for forming one or more lightly doped drain structures adjacent to the gate structure; thermally treating the semiconductor substrate at a first temperature lower than a threshold temperature, below which no substantial transient enhanced diffusion of the lightly doped drain structures occurs, for repairing damage to the semiconductor substrate caused by the ion implantation; forming sidewall spacers to sidewalls of the gate structure on the semiconductor substrate; and forming source and drain regions adjacent to the gate structure in the semiconductor substrate.
摘要翻译：在半导体衬底上形成MOS器件的方法包括以下步骤：在半导体衬底上形成栅极结构; 将离子注入到所述半导体衬底中，用于形成邻近所述栅极结构的一个或多个轻掺杂漏极结构; 在低于阈值温度的第一温度下对半导体衬底进行热处理，低于该阈值温度时，不会出现基本上暂时增加的轻掺杂漏极结构的扩散，以修复由离子注入引起的对半导体衬底的损伤; 在所述半导体衬底上形成所述栅极结构的侧壁的侧壁间隔物; 以及在所述半导体衬底中形成与所述栅极结构相邻的源区和漏区。

9. 发明申请

US20080237750A1 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US20080237750A1
公开(公告)日：2008-10-02
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

10. 发明授权

US07768072B2 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US07768072B2
公开(公告)日：2010-08-03
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L29/94
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

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