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1. 发明申请

US20130175504A1 OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS 有权
标题翻译：具有多个氧化物层的氧化物 - 氮氧化物堆
公开(公告)号：US20130175504A1
公开(公告)日：2013-07-11
申请号：US13436872
申请日：2012-03-31
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L29/775
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L21/28282 , H01L29/0673 , H01L29/0676 , H01L29/4234 , H01L29/42392 , H01L29/66795 , H01L29/7833 , H01L29/792 , H01L29/7926
摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
摘要翻译：描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

2. 发明授权

US07898852B1 Trapped-charge non-volatile memory with uniform multilevel programming 有权
标题翻译：具有均匀多电平编程的陷阱充电非易失性存储器
公开(公告)号：US07898852B1
公开(公告)日：2011-03-01
申请号：US12005803
申请日：2007-12-27
申请人： Sagy Levy , Krishnaswamy Ramkumar , Peter Voss
发明人： Sagy Levy , Krishnaswamy Ramkumar , Peter Voss
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C11/56 , H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Methods and apparatus for programming and sensing a bi-nitride layer trapped-charge memory device in one of a first and second programmed states or one of a first and second erased states, where the first and second programmed states correspond to first and second uniform trapped charge distributions of a first charge type and the first and second erased states correspond to first and second uniform trapped charge distributions of a second charge type.
摘要翻译：用于以第一和第二编程状态或第一和第二擦除状态中的一种编程和感测二氮化物层捕获电荷存储器件的方法和装置，其中第一和第二编程状态对应于第一和第二均匀捕获第一充电类型和第一和第二擦除状态的电荷分布对应于第二充电类型的第一和第二均匀俘获电荷分布。

3. 发明授权

US07670963B2 Single-wafer process for fabricating a nonvolatile charge trap memory device 有权
标题翻译：用于制造非易失性电荷陷阱存储器件的单晶片工艺
公开(公告)号：US07670963B2
公开(公告)日：2010-03-02
申请号：US11904513
申请日：2007-09-26
申请人： Krishnaswamy Ramkumar , Sagy Levy
发明人： Krishnaswamy Ramkumar , Sagy Levy
IPC分类号： H01L21/469
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833 , Y10S438/954
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。

4. 发明申请

US20090243001A1 Sequential deposition and anneal of a dielectic layer in a charge trapping memory device 有权
标题翻译：在电荷俘获存储器件中的介电层的顺序沉积和退火
公开(公告)号：US20090243001A1
公开(公告)日：2009-10-01
申请号：US12080166
申请日：2008-03-31
申请人： Krishnaswamy Ramkumar , Sagy Levy
发明人： Krishnaswamy Ramkumar , Sagy Levy
IPC分类号： H01L29/00 , H01L21/31
CPC分类号： H01L21/28282 , H01L21/3145
摘要： Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.
摘要翻译：重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。在一个具体实施方案中，进行包括NH 3或ND 3环境，随后是N 2 O或NO环境的两步退火。在一个实施例中，采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层，这在沉积过程中具有非常高的特性。在特定实施例中，顺序沉积 - 退火操作提供退火的第一介电层，第二介电层可以在其上基本上保持不退火。

5. 发明申请

US20090011609A1 RADICAL OXIDATION PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE 有权
标题翻译：用于制造非易失性电荷捕获存储器件的放射性氧化方法
公开(公告)号：US20090011609A1
公开(公告)日：2009-01-08
申请号：US12197466
申请日：2008-08-25
申请人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
发明人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括提供其上设置有电荷捕获层的衬底。然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡电介质层。

6. 发明授权

US08993453B1 Method of fabricating a nonvolatile charge trap memory device 有权
标题翻译：制造非易失性电荷陷阱存储器件的方法
公开(公告)号：US08993453B1
公开(公告)日：2015-03-31
申请号：US13620071
申请日：2012-09-14
申请人： Krishnaswamy Ramkumar , Jeong Byun , Sagy Levy
发明人： Krishnaswamy Ramkumar , Jeong Byun , Sagy Levy
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833
摘要： A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
摘要翻译：描述了一种用于制造非易失性电荷陷阱存储器件及其装置的方法。在一个实施例中，该方法包括在氧化室中提供衬底，其中衬底包括第一暴露的晶体面和第二暴露的晶面，并且其中第一暴露的晶面的晶体取向不同于第二次暴露的晶面。然后对基板进行自由基氧化处理，以在第一暴露的晶面上形成电介质层的第一部分，在第二暴露的晶面上形成电介质层的第二部分，其中电介质的第一部分的厚度层大致等于电介质层的第二部分的厚度。

7. 发明授权

US08871595B2 Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
标题翻译：集成非易失性电荷陷阱存储器件和逻辑CMOS器件
公开(公告)号：US08871595B2
公开(公告)日：2014-10-28
申请号：US13436878
申请日：2012-03-31
申请人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
发明人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
IPC分类号： H01L21/8239
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/28282 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66833 , H01L29/7836 , H01L29/7843 , H01L29/792 , H01L29/7926
摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

8. 发明授权

US08643124B2 Oxide-nitride-oxide stack having multiple oxynitride layers 有权
标题翻译：具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠
公开(公告)号：US08643124B2
公开(公告)日：2014-02-04
申请号：US13007533
申请日：2011-01-14
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L21/336
CPC分类号： H01L29/512 , C23C16/0272 , C23C16/308 , G11C16/0466 , H01L21/0214 , H01L21/02271 , H01L21/28282 , H01L21/3145 , H01L29/518 , H01L29/66833 , H01L29/7833 , H01L29/792
摘要： A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.
摘要翻译：提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。还公开了其他实施例。

9. 发明授权

US08592891B1 Methods for fabricating semiconductor memory with process induced strain 有权
标题翻译：用工艺诱导应变制造半导体存储器的方法
公开(公告)号：US08592891B1
公开(公告)日：2013-11-26
申请号：US13539463
申请日：2012-07-01
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Byun
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Byun
IPC分类号： H01L29/76
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.
摘要翻译：提供了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有设置在沟道区上方的氧化氮化物 - 氮化物 - 氧化物（ONNO）堆的存储晶体管。 ONNO堆叠包括设置在沟道区上方的隧道介电层，设置在隧道介电层上方的多层电荷捕获区，以及设置在多层电荷俘获区上方的阻挡介质层。多层电荷捕获区域包括基本上无陷阱层，其包含富含氧的氮化物和设置在无阱层之上的陷阱致密层。半导体器件还包括应变诱导结构，其包括设置在ONNO堆叠附近的应变诱导层，以增加多层电荷俘获区域的电荷保留。还公开了其他实施例。

10. 发明申请

US20090032863A1 Nitridation oxidation of tunneling layer for improved SONOS speed and retention 有权
标题翻译：隧道层的氮化氧化提高了SONOS的速度和保留时间
公开(公告)号：US20090032863A1
公开(公告)日：2009-02-05
申请号：US12005813
申请日：2007-12-27
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick B. Jenne
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick B. Jenne
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/3143 , H01L29/4234 , H01L29/4916 , H01L29/512 , H01L29/513 , H01L29/518
摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.
摘要翻译：一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。该方法提供了SONOS型设备中改进的存储器窗口。在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

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