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1. 发明授权

US09449831B2 Oxide-nitride-oxide stack having multiple oxynitride layers 有权
标题翻译：具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠
公开(公告)号：US09449831B2
公开(公告)日：2016-09-20
申请号：US13436872
申请日：2012-03-31
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L21/28 , G11C16/04 , H01L29/792 , B82Y10/00 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L21/28282 , H01L29/0673 , H01L29/0676 , H01L29/4234 , H01L29/42392 , H01L29/66795 , H01L29/7833 , H01L29/792 , H01L29/7926
摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
摘要翻译：描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

2. 发明授权

US09299568B2 SONOS ONO stack scaling 有权
标题翻译： SONOS ONO堆栈缩放
公开(公告)号：US09299568B2
公开(公告)日：2016-03-29
申请号：US13539461
申请日：2012-07-01
申请人： Fredrick Jenne , Sagy Levy , Krishnaswamy Ramkumar
发明人： Fredrick Jenne , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L21/336 , H01L21/28 , H01L21/314 , H01L29/51 , H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L21/02532 , H01L21/02595 , H01L21/02667 , H01L21/28282 , H01L21/3105 , H01L21/3143 , H01L29/04 , H01L29/16 , H01L29/42364 , H01L29/4916 , H01L29/513 , H01L29/515 , H01L29/518 , H01L29/66833
摘要： A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
摘要翻译：提供了一种缩放非易失性俘获电荷存储器件及其制造的器件的方法。在一个实施例中，该方法包括形成包括电连接衬底中的源极区域和漏极区域的多晶硅沟道区域。通过氧化衬底以在沟道区域上的衬底上形成隧穿层以形成氧化膜并氮化氧化膜。在隧道层上形成包含富氧的第一层和无氧的第二层的多层电荷俘获层，以及沉积在多层电荷俘获层上的阻挡层。在一个实施方案中，该方法还包括稀释的湿氧化以致密集沉积的阻塞氧化物并氧化贫氧的第二层的一部分。

3. 发明申请

US20110248332A1 Oxide-Nitride-Oxide Stack Having Multiple Oxynitride Layers 有权
标题翻译：具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠
公开(公告)号：US20110248332A1
公开(公告)日：2011-10-13
申请号：US13007533
申请日：2011-01-14
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/512 , C23C16/0272 , C23C16/308 , G11C16/0466 , H01L21/0214 , H01L21/02271 , H01L21/28282 , H01L21/3145 , H01L29/518 , H01L29/66833 , H01L29/7833 , H01L29/792
摘要： A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.
摘要翻译：提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氮氧化物层上的贫氧的第二氧氮化物层第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。还公开了其他实施例。

4. 发明申请

US20130175504A1 OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS 有权
标题翻译：具有多个氧化物层的氧化物 - 氮氧化物堆
公开(公告)号：US20130175504A1
公开(公告)日：2013-07-11
申请号：US13436872
申请日：2012-03-31
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L29/775
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L21/28282 , H01L29/0673 , H01L29/0676 , H01L29/4234 , H01L29/42392 , H01L29/66795 , H01L29/7833 , H01L29/792 , H01L29/7926
摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
摘要翻译：描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

5. 发明授权

US08871595B2 Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
标题翻译：集成非易失性电荷陷阱存储器件和逻辑CMOS器件
公开(公告)号：US08871595B2
公开(公告)日：2014-10-28
申请号：US13436878
申请日：2012-03-31
申请人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
发明人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
IPC分类号： H01L21/8239
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/28282 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66833 , H01L29/7836 , H01L29/7843 , H01L29/792 , H01L29/7926
摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

6. 发明授权

US08643124B2 Oxide-nitride-oxide stack having multiple oxynitride layers 有权
标题翻译：具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠
公开(公告)号：US08643124B2
公开(公告)日：2014-02-04
申请号：US13007533
申请日：2011-01-14
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L21/336
CPC分类号： H01L29/512 , C23C16/0272 , C23C16/308 , G11C16/0466 , H01L21/0214 , H01L21/02271 , H01L21/28282 , H01L21/3145 , H01L29/518 , H01L29/66833 , H01L29/7833 , H01L29/792
摘要： A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.
摘要翻译：提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。还公开了其他实施例。

7. 发明授权

US09716153B2 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region 有权
公开(公告)号：US09716153B2
公开(公告)日：2017-07-25
申请号：US13539459
申请日：2012-07-01
申请人： Sagy Levy , Fredrick Jenne , Krishnaswamy Ramkumar
发明人： Sagy Levy , Fredrick Jenne , Krishnaswamy Ramkumar
IPC分类号： H01L29/792 , H01L29/40 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/786 , H01L29/04 , H01L29/06 , H01L29/16
CPC分类号： H01L29/408 , H01L21/28282 , H01L29/04 , H01L29/0676 , H01L29/16 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/785 , H01L29/78696 , H01L29/792 , H01L29/7926
摘要： Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.

8. 发明申请

US20130178031A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 有权
标题翻译：非挥发性电荷捕获存储器件和逻辑CMOS器件的集成
公开(公告)号：US20130178031A1
公开(公告)日：2013-07-11
申请号：US13436878
申请日：2012-03-31
申请人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
发明人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/28282 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66833 , H01L29/7836 , H01L29/7843 , H01L29/792 , H01L29/7926
摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

9. 发明申请

US20090179253A1 Oxide-nitride-oxide stack having multiple oxynitride layers 审中-公开
标题翻译：具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠
公开(公告)号：US20090179253A1
公开(公告)日：2009-07-16
申请号：US11811958
申请日：2007-06-13
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/0214 , C23C16/0272 , C23C16/308 , G11C16/0466 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/3145 , H01L27/11568 , H01L29/40117 , H01L29/518 , H01L29/7833 , H01L29/792
摘要： A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.
摘要翻译：提供了包括具有多层电荷存储层的氧化物 - 氧化物 - 氧化物（ONO）结构的半导体器件及其形成方法。通常，该方法包括：（i）形成ONO结构的第一氧化物层; （ii）在所述第一氧化物层的表面上形成包含氮化物的多层电荷存储层; 和（iii）在多层电荷存储层的表面上形成ONO结构的第二氧化物层。优选地，电荷存储层包括至少两个氧氮，氮和/或硅具有不同化学计量组成的氮氧化硅层。更优选地，ONO结构是氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）结构的一部分，并且半导体器件是SONOS存储晶体管。还公开了其他实施例。

10. 发明授权

US08710578B2 SONOS stack with split nitride memory layer 有权
标题翻译： SONOS堆叠带有划痕的氮化物存储层
公开(公告)号：US08710578B2
公开(公告)日：2014-04-29
申请号：US13431069
申请日：2012-03-27
申请人： Fredrick Jenne , Krishnaswamy Ramkumar
发明人： Fredrick Jenne , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28282 , H01L29/513 , H01L29/785 , H01L29/7926
摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.
摘要翻译：描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。还公开了其他实施例。

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