专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 再颁专利

USRE37103E1 Graphic processing apparatus utilizing improved data transfer to reduce memory size 失效
标题翻译：利用改进的数据传输来减少存储器大小的图形处理装置
公开(公告)号：USRE37103E1
公开(公告)日：2001-03-20
申请号：US07985141
申请日：1992-12-03
申请人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
发明人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
IPC分类号： G06F1900
CPC分类号： G09G5/393 , G06T1/60
摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
摘要翻译：存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器提供并行数据处理。在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

2. 发明授权

US4975857A Graphic processing apparatus utilizing improved data transfer to reduce memory size 失效
标题翻译：利用改进的数据传输来减少存储器大小的图形处理装置
公开(公告)号：US4975857A
公开(公告)日：1990-12-04
申请号：US302332
申请日：1989-01-27
申请人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
发明人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
IPC分类号： G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/36 , G06T1/20 , G06T1/60 , G09G5/393
CPC分类号： G09G5/393 , G06T1/60
摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
摘要翻译：存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器提供并行数据处理。在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

3. 再颁专利

USRE39529E1 Graphic processing apparatus utilizing improved data transfer to reduce memory size 有权
标题翻译：利用改进的数据传输来减少存储器大小的图形处理装置
公开(公告)号：USRE39529E1
公开(公告)日：2007-03-27
申请号：US09536646
申请日：2000-03-28
申请人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
发明人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
IPC分类号： G09G5/39
CPC分类号： G09G5/393
摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
摘要翻译：存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器提供并行数据处理。在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

4. 发明申请

US20100180140A1 DATA PROCESSING SYSTEM AND IMAGE PROCESSING SYSTEM 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US20100180140A1
公开(公告)日：2010-07-15
申请号：US12731442
申请日：2010-03-25
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/12
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

5. 发明申请

US20080168295A1 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US20080168295A1
公开(公告)日：2008-07-10
申请号：US11826136
申请日：2007-07-13
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/10 , G06F1/12 , G06F1/06
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

6. 发明授权

US07254737B2 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US07254737B2
公开(公告)日：2007-08-07
申请号：US10897022
申请日：2004-07-23
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

7. 发明授权

US07082224B2 Statistic calculating method using a template and corresponding sub-image to determine similarity based on sum of squares thresholding 失效
标题翻译：使用模板和相应子图像的统计计算方法根据平方和阈值确定相似度
公开(公告)号：US07082224B2
公开(公告)日：2006-07-25
申请号：US11060400
申请日：2005-02-18
申请人： Mitsuji Ikeda , Syoji Yoshida , Keisuke Nakashima , Koyo Katsura , Shigeru Shibukawa , Haruo Yoda , Takashi Hotta
发明人： Mitsuji Ikeda , Syoji Yoshida , Keisuke Nakashima , Koyo Katsura , Shigeru Shibukawa , Haruo Yoda , Takashi Hotta
IPC分类号： G06K9/64
CPC分类号： G06K9/6203 , G06T7/20
摘要： An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image. Normalized correlation coefficient calculating means calculate a normalized correlation coefficient on the basis of the sum of image data values of pixels in the template image and the sum of image data values of pixels in the first rectangular region in the search image, or the sum of squares of image data values of pixels in the template image and the sum of squares of image data values of pixels in the first rectangular region in the search image.
摘要翻译：一种用于计算通过使用模板图像中的像素的图像数据值和相应于模板图像的包括在搜索图像中的子图像中的像素的图像数据值而用作相似性评估度量的归一化相关系数的装置，具有存储器其存储搜索图像中的像素的图像数据值;以及计算装置，其计算模板图像中的像素的图像数据值的和和搜索图像中的第一矩形区域中的像素的图像数据值之和，或者模板图像中的像素的图像数据值的平方和搜索图像中的第一矩形区域中的像素的图像数据值的平方和。归一化相关系数计算装置基于模板图像中的像素的图像数据值之和和搜索图像中的第一矩形区域中的像素的图像数据值之和或平方和来计算归一化相关系数的模板图像中的像素的图像数据值和搜索图像中的第一矩形区域中的像素的图像数据值的平方和。

8. 发明授权

US07064756B2 Data processing apparatus and shading apparatus 失效
公开(公告)号：US07064756B2
公开(公告)日：2006-06-20
申请号：US10947275
申请日：2004-09-23
申请人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
发明人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
IPC分类号： G06T11/00
CPC分类号： G06T1/60 , G06T11/40 , G06T15/50 , G06T15/80
摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.

9. 发明授权

US07006134B1 Pen type input device with camera 失效
标题翻译：带相机的笔型输入设备
公开(公告)号：US07006134B1
公开(公告)日：2006-02-28
申请号：US09763823
申请日：1999-08-12
申请人： Toshifumi Arai , Kimiyoshi Machii , Koyo Katsura , Hideyuki Watanabe
发明人： Toshifumi Arai , Kimiyoshi Machii , Koyo Katsura , Hideyuki Watanabe
IPC分类号： H04N5/228
CPC分类号： G06K9/228 , G06F3/03545
摘要： A pen type input device with a camera has improved usability as a result in improved construction of the device. The pen type input device with the camera is adapted for use in detecting both of a horizontally elongated object and a vertically elongated object. On the other hand, means for pointing to the object and the process content simultaneously, and further means for detecting the fact that the user is pointing to the object in an erroneous manner and for teaching a correct manner of pointing to the object depending thereon are provided.
摘要翻译：具有相机的笔式输入装置改善了可用性，因此改进了装置的结构。具有相机的笔型输入装置适用于检测水平细长物体和垂直细长物体。另一方面，用于同时指向对象和处理内容的装置，以及用于以错误的方式检测用户指向对象并根据其指示正确方式指向对象的事实的另外的装置是：提供。

10. 发明授权

US06954206B2 Data processor having unified memory architecture using register to optimize memory access 失效
标题翻译：具有使用寄存器的统一存储器架构的数据处理器来优化存储器
公开(公告)号：US06954206B2
公开(公告)日：2005-10-11
申请号：US10669562
申请日：2003-09-25
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F13/14 , G06F13/16 , G06F13/18 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/36 , G09G5/39
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求由存储器200。当CPU总线310的访问结束时，存储器控制器400重启在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式