专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5300798A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5300798A
公开(公告)日：1994-04-05
申请号：US978293
申请日：1992-11-17
申请人： Kouichi Yamazaki , Setsuo Ogura , Kazuyuki Kamegaki , Kenya Yamauchi , Yukinori Kitamura , Tuyoshi Nagase
发明人： Kouichi Yamazaki , Setsuo Ogura , Kazuyuki Kamegaki , Kenya Yamauchi , Yukinori Kitamura , Tuyoshi Nagase
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/528 , H01L27/02
CPC分类号： H01L23/5286 , H01L27/0207 , H01L2924/0002 , H01L2924/3011
摘要： When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main extended direction prescribed to be the X-direction, and wirings in the second wiring layer, in which wirings have their main extended direction prescribed to be the Y-direction, formed over the first wiring layer. Wirings in the third wiring layer, in which wirings have their main extended direction prescribed to be the same as the wirings in the second wiring layer, formed over the second wiring layer, together with wirings in the first and second wiring layer, are used as signal wirings between functional blocks, while the wirings in the third wiring layer are used as power supply wirings for providing power supply to functional blocks. As the power supply paths to functional blocks, a plurality of power supply wirings are branched off from the power supply electrode such as a power supply pad and terminated there. The power supply electrode on the high voltage side and the power supply electrode on the low voltage side are disposed separately at opposing edge portions of the semiconductor substrate and the power supply wirings proceeding therefrom to their target functional blocks are bent in the vicinity of the edge portion of the semiconductor substrate and therefrom extended straight to the target points.
摘要翻译：当具有三层以上的布线结构的半导体集成电路器件被分级地考虑为多个功能块的集合时，每个功能块通过布线在第一布线层中的布线内部连接，其中布线具有其主要延伸方向规定为X方向，并且在第一布线层上形成第二布线层中的布线，其中布线的主要延伸方向规定为Y方向。将在第二布线层中形成的与第二布线层中的配线相同的布线的第三布线层中的布线与第一布线层和第二布线层中的布线一起用作布线层的布线功能块之间的信号布线，而第三布线层中的布线用作向功能块提供电源的电源布线。作为对功能块的供电路径，多个电源配线从诸如电源焊盘的电源电极分支，并在那里终止。高电压侧的电源电极和低电压侧的电源电极分别设置在半导体基板的相对的边缘部分，并且从其到达其目标功能块的电源布线在边缘附近弯曲半导体衬底的一部分并且直接延伸到目标点。

2. 发明授权

US4857987A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4857987A
公开(公告)日：1989-08-15
申请号：US246924
申请日：1988-09-19
申请人： Setsuo Ogura , Kazuyuki Kamegaki , Kouichi Yamazaki , Hideo Miyazaki , Yukinori Kitamura , Shirou Mayuzumi
发明人： Setsuo Ogura , Kazuyuki Kamegaki , Kouichi Yamazaki , Hideo Miyazaki , Yukinori Kitamura , Shirou Mayuzumi
IPC分类号： H01L27/082 , H01L21/768 , H01L21/8226 , H01L23/522 , H01L27/02 , H01L29/41
CPC分类号： H01L27/0233
摘要： Herein disclosed is a semiconductor device including a plurality of IIL elements which are electrically connected by a plurality of first wirings arranged generally parallel with one another and a plurality of second wirings arranged generally parallel with one another and extended in different direction to the first wirings.
摘要翻译：这里公开的是一种半导体器件，其包括多个IIL元件，它们通过彼此平行布置的多个第一布线电连接，并且多个第二布线大体上彼此平行地布置并沿与第一布线不同的方向延伸。

3. 发明授权

US5132806A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5132806A
公开(公告)日：1992-07-21
申请号：US538448
申请日：1990-06-15
申请人： Yukinori Kitamura , Setsuo Ogura , Shiro Mayuzumi , Shunji Mori , Toshiyuki Fukamachi , Yuji Kobayashi , Kouichi Yamazaki , Makoto Furihata , Kazuyuki Kamegaki
发明人： Yukinori Kitamura , Setsuo Ogura , Shiro Mayuzumi , Shunji Mori , Toshiyuki Fukamachi , Yuji Kobayashi , Kouichi Yamazaki , Makoto Furihata , Kazuyuki Kamegaki
IPC分类号： H01L21/761 , H01L21/822 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/082 , H04N9/79
CPC分类号： H04N9/79 , H01L27/0207 , H01L2224/05554 , H01L2224/45147 , H01L2224/49113 , H01L2224/49171 , H01L2924/1301 , H01L2924/1305 , Y10S257/906
摘要： Disclosed is a novel semiconductor integrated circuit device for use in a color VTR (Video Tape Recorder). Concretely, the semiconductor integrated circuit device comprises a substantially rectangular semiconductor chip which has a principal surface, a luminance signal processing unit and a color signal processing unit which are disposed at the positions of the principal surface opposing to each other, and a semiconductor region which is provided in the interspace of the principal surface between the luminance signal and color signal processing units opposing to each other and which is supplied with a bias stable A.C.-wise. Further, the semiconductor region is located substantially at the central portion of the semiconductor chip and is extended so as to intersect with one set of opposing sides of the rectangular semiconductor chip.
摘要翻译：公开了一种用于彩色VTR（录像机）的新型半导体集成电路装置。具体地，半导体集成电路器件包括：主体表面的基本上矩形的半导体芯片，设置在彼此相对的主表面的位置处的亮度信号处理单元和颜色信号处理单元;以及半导体区域，设置在彼此相对的亮度信号和颜色信号处理单元之间的主表面的间隙中，并且被提供有偏置稳定的交流方式。此外，半导体区域基本上位于半导体芯片的中心部分并且被延伸以与矩形半导体芯片的一组相对侧相交。

4. 发明授权

US4505766A Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition 失效
标题翻译：利用同时扩散和外延沉积制造半导体器件的方法
公开(公告)号：US4505766A
公开(公告)日：1985-03-19
申请号：US491543
申请日：1983-05-04
申请人： Shuzo Nagumo , Setsuo Ogura , Yukinori Kitamura
发明人： Shuzo Nagumo , Setsuo Ogura , Yukinori Kitamura
IPC分类号： H01L27/04 , H01L21/22 , H01L21/331 , H01L21/74 , H01L21/822 , H01L21/8222 , H01L27/02 , H01L27/06 , H01L27/08 , H01L29/73 , H01L29/93 , H01L21/20
CPC分类号： H01L21/2205 , H01L21/74 , H01L27/0244 , H01L27/0647 , H01L27/0805 , H01L29/93 , Y10S438/901
摘要： A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.
摘要翻译：半导体器件具有第一导电类型的扩散层，其延伸到第二导电类型的掩埋层，其以从外延生长的第二导电类型的半导体层的表面的一部分延伸的方式形成通过第二导电类型的掩埋层的第一导电类型的半导体衬底。半导体结电容由第一导电类型的扩散层和第二导电类型的掩埋层形成，并且控制要引入到第二导电类型的掩埋层中的杂质的浓度。

5. 发明授权

US4536784A Semiconductor device having a junction capacitance, an integrated injection logic circuit and a transistor in a semiconductor body 失效
标题翻译：具有结电容的半导体器件，集成注入逻辑电路和半导体本体中的晶体管
公开(公告)号：US4536784A
公开(公告)日：1985-08-20
申请号：US541445
申请日：1983-10-13
申请人： Shuzo Nagumo , Setsuo Ogura , Yukinori Kitamura
发明人： Shuzo Nagumo , Setsuo Ogura , Yukinori Kitamura
IPC分类号： H01L27/04 , H01L21/22 , H01L21/331 , H01L21/74 , H01L21/822 , H01L21/8222 , H01L27/02 , H01L27/06 , H01L27/08 , H01L29/73 , H01L29/93 , H01L29/92
CPC分类号： H01L21/2205 , H01L21/74 , H01L27/0244 , H01L27/0647 , H01L27/0805 , H01L29/93 , Y10S438/901
摘要： A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.
摘要翻译：半导体器件具有第一导电类型的扩散层，其延伸到第二导电类型的掩埋层，其以从外延生长的第二导电类型的半导体层的表面的一部分延伸的方式形成通过第二导电类型的掩埋层的第一导电类型的半导体衬底。半导体结电容由第一导电类型的扩散层和第二导电类型的掩埋层形成，并且控制要引入到第二导电类型的掩埋层中的杂质的浓度。

6. 发明授权

US4697102A Bipolar logic circuit having two multi-emitter transistors with an emitter of one connected to the collector of the other to prevent saturation 失效
标题翻译：双极逻辑电路具有两个多发射极晶体管，其发射极连接到另一个的集电极以防止饱和
公开(公告)号：US4697102A
公开(公告)日：1987-09-29
申请号：US737872
申请日：1985-05-28
申请人： Takahiro Okabe , Makoto Hayashi , Katuhiro Morisuye , Tomoyuki Watanabe , Katsuyoshi Washio , Setsuo Ogura , Makoto Furihata , Shizuo Kondo
发明人： Takahiro Okabe , Makoto Hayashi , Katuhiro Morisuye , Tomoyuki Watanabe , Katsuyoshi Washio , Setsuo Ogura , Makoto Furihata , Shizuo Kondo
IPC分类号： H03K19/00 , H03K19/013 , H03K19/082
CPC分类号： H03K19/001 , H03K19/013
摘要： A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed. A further feature is the provision of a logic circuit which is highly integrated and which consumes reduced amounts of electric power, while maintaining high-speed performance of the TTL circuit, by substituting a multi-collector transistor that reversely operates for an inverter portion of the TTL circuit.
摘要翻译：提供了一种逻辑电路，其包括第一多发射极晶体管，其发射极耦合到一组第一输入线，第一晶体管的基极耦合到所述第一多发射极晶体管的集电极。第二晶体管还设置有其基极耦合到所述第一晶体管的集电极，所述第二晶体管具有与所述第一多发射极晶体管的极性相反的极性。第二多发射极晶体管与其基极耦合，耦合到所述第二晶体管的集电极，并且其发射极耦合到一组第二输入线，并且第三晶体管与其基极连接，耦合到所述第二多晶体管的集电极，发射极晶体管，其集电极耦合到输出线。所述第一多发射极晶体管的集电极耦合到所述第二多发射极晶体管的发射极，以便吸收存储在晶体管中的少数载流子。该功能显着提高了电路工作速度。另一个特征是提供了一种高度集成的逻辑电路，并且通过将反向工作的多集电极晶体管替换为逆变器部分的多集电极晶体管，同时维持TTL电路的高速性能，从而消耗了较少的电功率 TTL电路。

7. 发明授权

US4670859A Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US4670859A
公开(公告)日：1987-06-02
申请号：US704412
申请日：1985-02-22
申请人： Makoto Furihata , Setsuo Ogura , Shizuo Kondo , Eiji Minamimura
发明人： Makoto Furihata , Setsuo Ogura , Shizuo Kondo , Eiji Minamimura
IPC分类号： G11C17/00 , H03K19/00 , H03K19/091
CPC分类号： H03K19/091 , H03K19/001
摘要： A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.
摘要翻译：消耗少量电力的大规模的逻辑电路包括由IIL电路形成的多个ROM部分。输入信号线通常用于将输入信号发送到ROM部分。多个ROM部分由ROM选择信号选择性地操作，并且从所选择的ROM部分获得对应于输入信号的输出。为了选择多个ROM部分中的特定ROM部分，构成所选择的ROM部分的IIL电路的逆npn晶体管的发射极被呈现为地电位。同时，未选择的ROM部分中的IIL电路的逆npn晶体管的发射极保持在浮置状态。这使得可以以非常简单的结构获得消耗少量电力的逻辑电路，因为未选择的ROM部分不消耗电力。

8. 发明授权

US4804940A Resistor and electron device employing the same 失效
标题翻译：电阻器和采用该电阻器的电子器件
公开(公告)号：US4804940A
公开(公告)日：1989-02-14
申请号：US843666
申请日：1986-03-25
申请人： Akira Takigawa , Shizuo Kondo , Masumi Kasahara , Toshinori Hirashima , Mikio Haijima , Setsuo Ogura , Osamu Takada , Yoshiki Akamatsu
发明人： Akira Takigawa , Shizuo Kondo , Masumi Kasahara , Toshinori Hirashima , Mikio Haijima , Setsuo Ogura , Osamu Takada , Yoshiki Akamatsu
IPC分类号： H01C7/00 , H01L21/02 , H03M1/76 , H03M1/36 , H03M1/74
CPC分类号： H01L28/20 , H01C7/006 , H03M1/765
摘要： A resistor is provided with a plurality of turn parts whose corners have an obtuse flexional angle in order to improve the relative resistance precision. A ladder resistor can be formed with a plurality of such resistors connected in series, and various electronic devices are formed employing the ladder resistor.
摘要翻译：电阻器设置有多个转弯部分，其拐角具有钝的弯曲角度，以便提高相对电阻精度。梯形电阻器可以形成有串联连接的多个这样的电阻器，并且使用梯形电阻器形成各种电子器件。

9. 发明授权

US4725745A Bi-MOS PLA 失效
公开(公告)号：US4725745A
公开(公告)日：1988-02-16
申请号：US643260
申请日：1984-08-22
申请人： Shizuo Kondo , Setsuo Ogura , Eiji Minamimura , Makoto Furihata
发明人： Shizuo Kondo , Setsuo Ogura , Eiji Minamimura , Makoto Furihata
IPC分类号： H01L27/112 , H03K19/0944 , H03K19/177 , H03K19/02 , G06F7/38 , H03K19/091
CPC分类号： H03K19/09448 , H01L27/112 , H03K19/17708
摘要： An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.
摘要翻译：形成在单个硅芯片内的集成可编程逻辑阵列包括逻辑乘积门阵列和逻辑求和门阵列的组合。逻辑积门阵列配备有多个MIS场效应晶体管，其栅极由多个输入信号选择性地驱动。这些晶体管的源极 - 漏极路径串联连接。逻辑求和门阵列配备有多个并联连接的集电极 - 发射极路径的反向双极晶体管。

10. 发明授权

US4659947A PLA with forward-conduction bipolar "and" array and I.sup.2 L "OR" array 失效
标题翻译： PLA与前导双极“和”阵列和I2L“OR”阵列
公开(公告)号：US4659947A
公开(公告)日：1987-04-21
申请号：US665385
申请日：1984-10-26
申请人： Setsuo Ogura , Shizuo Kondo , Eiji Minamimura , Makoto Furihata
发明人： Setsuo Ogura , Shizuo Kondo , Eiji Minamimura , Makoto Furihata
IPC分类号： H03K19/091 , H03K19/177 , H03K19/082
CPC分类号： H03K19/17708
摘要： An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array.The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.
摘要翻译：形成在单个硅芯片内的集成可编程逻辑阵列包括NAND或与门阵列和NOR或OR门阵列的组合。 NAND或与门阵列包括多个双极晶体管，其被驱动以通过多个输入信号在正向工作，以及设置在双极晶体管的集电极和输出信号线之间的多个肖特基势垒二极管。 NOR或OR门阵列包括多个其它双极晶体管，其被驱动以通过来自NAND或与门阵列的多个输出信号在向后方向上工作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式