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1. 发明申请

US20110272753A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110272753A1
公开(公告)日：2011-11-10
申请号：US13144744
申请日：2009-10-23
申请人： Kota Funayama , Hiraku Chakihara , Yasushi Ishii
发明人： Kota Funayama , Hiraku Chakihara , Yasushi Ishii
IPC分类号： H01L29/792 , H01L21/8239 , H01L21/336 , H01L27/06 , H01L21/28
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L23/53214 , H01L23/53257 , H01L23/535 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11575 , H01L29/0653 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.
摘要翻译：在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG）通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM）电极（MG）并且电连接到存储栅电极（MG）。由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

2. 发明授权

US08633530B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08633530B2
公开(公告)日：2014-01-21
申请号：US13144744
申请日：2009-10-23
申请人： Kota Funayama , Hiraku Chakihara , Yasushi Ishii
发明人： Kota Funayama , Hiraku Chakihara , Yasushi Ishii
IPC分类号： H01L21/28 , H01L29/792 , H01L21/336 , H01L27/06
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L23/53214 , H01L23/53257 , H01L23/535 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11575 , H01L29/0653 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.
摘要翻译：在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG）通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM）电极（MG）并且电连接到存储栅电极（MG）。由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

3. 发明申请

US20120292679A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120292679A1
公开(公告)日：2012-11-22
申请号：US13468992
申请日：2012-05-10
申请人： Kota FUNAYAMA , Hiraku Chakihara , Yasushi Ishii
发明人： Kota FUNAYAMA , Hiraku Chakihara , Yasushi Ishii
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L27/11563 , G11C16/0466 , H01L21/28282 , H01L27/1052 , H01L27/11517 , H01L27/11565 , H01L27/11568 , H01L28/40 , H01L29/4234 , H01L29/66477 , H01L29/66833 , H01L29/792
摘要： A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.
摘要翻译：在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜一部分。电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极薄膜作为记忆栅电极。上部电极的杂质浓度高于记忆栅电极的浓度。

4. 发明授权

US09093319B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09093319B2
公开(公告)日：2015-07-28
申请号：US13468992
申请日：2012-05-10
申请人： Kota Funayama , Hiraku Chakihara , Yasushi Ishii
发明人： Kota Funayama , Hiraku Chakihara , Yasushi Ishii
IPC分类号： H01L29/94 , H01L27/115 , H01L27/105 , H01L21/28 , H01L49/02 , H01L29/423 , H01L29/792 , G11C16/04 , H01L29/66
CPC分类号： H01L27/11563 , G11C16/0466 , H01L21/28282 , H01L27/1052 , H01L27/11517 , H01L27/11565 , H01L27/11568 , H01L28/40 , H01L29/4234 , H01L29/66477 , H01L29/66833 , H01L29/792
摘要： A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.
摘要翻译：在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜一部分。电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极薄膜作为记忆栅电极。上部电极的杂质浓度高于记忆栅电极的浓度。

5. 发明授权

US08969943B2 Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US08969943B2
公开(公告)日：2015-03-03
申请号：US13302184
申请日：2011-11-22
申请人： Koichi Toba , Yasushi Ishii , Hiraku Chakihara , Kota Funayama , Yoshiyuki Kawashima , Takashi Hashimoto
发明人： Koichi Toba , Yasushi Ishii , Hiraku Chakihara , Kota Funayama , Yoshiyuki Kawashima , Takashi Hashimoto
IPC分类号： H01L29/792 , H01L21/28 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11573 , H01L29/42344 , H01L29/792
摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
摘要翻译：提供了具有非易失性存储器的半导体器件，其具有改进的特性。半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

6. 发明授权

US08951860B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08951860B2
公开(公告)日：2015-02-10
申请号：US13612630
申请日：2012-09-12
申请人： Yasushi Ishii , Hiraku Chakihara , Takahiro Maruyama , Akihiro Nakae
发明人： Yasushi Ishii , Hiraku Chakihara , Takahiro Maruyama , Akihiro Nakae
IPC分类号： H01L21/336 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/792 , H01L27/115 , H01L49/02
CPC分类号： H01L21/28282 , H01L27/11573 , H01L28/60 , H01L29/42344 , H01L29/66833 , H01L29/792 , H01L2223/54426 , H01L2223/5446
摘要： The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.
摘要翻译：本发明提高了具有分裂栅极结构的非易失性存储单元的半导体器件的生产成本。存储垫的端部被覆盖的下层抗蚀剂膜的电平差为绅士，改善了形成在下层抗蚀剂膜上的抗蚀剂中间层的厚度的均匀性，并且防止了局部厚度减小或消失通过在形成在半导体衬底的存储单元区域中的每个选择栅极上形成氧化硅膜和氮化硅膜之后，在位于最外侧的选择栅电极上去除氧化硅膜和氮化硅膜（虚拟单元区域）。

7. 发明授权

US08373216B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08373216B2
公开(公告)日：2013-02-12
申请号：US12913759
申请日：2010-10-27
申请人： Hiraku Chakihara , Yasushi Ishii
发明人： Hiraku Chakihara , Yasushi Ishii
IPC分类号： H01L29/94
CPC分类号： H01L27/11575 , H01L21/28273 , H01L21/28282 , H01L21/823443 , H01L21/823462 , H01L21/823835 , H01L27/0922 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11548 , H01L27/11565 , H01L27/11568 , H01L28/40 , H01L29/0649 , H01L29/42324 , H01L29/42328 , H01L29/4234 , H01L29/42344 , H01L29/4975 , H01L29/6653 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7881 , H01L29/792
摘要： Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.
摘要翻译：提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

8. 发明申请

US20110095348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110095348A1
公开(公告)日：2011-04-28
申请号：US12913759
申请日：2010-10-27
申请人： Hiraku CHAKIHARA , Yasushi Ishii
发明人： Hiraku CHAKIHARA , Yasushi Ishii
IPC分类号： H01L29/94 , H01L21/336 , H01L27/088
CPC分类号： H01L27/11575 , H01L21/28273 , H01L21/28282 , H01L21/823443 , H01L21/823462 , H01L21/823835 , H01L27/0922 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11548 , H01L27/11565 , H01L27/11568 , H01L28/40 , H01L29/0649 , H01L29/42324 , H01L29/42328 , H01L29/4234 , H01L29/42344 , H01L29/4975 , H01L29/6653 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7881 , H01L29/792
摘要： Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.
摘要翻译：提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

9. 发明授权

US08395203B2 Semiconductor device and a manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08395203B2
公开(公告)日：2013-03-12
申请号：US12951012
申请日：2010-11-20
申请人： Hiraku Chakihara , Yasushi Ishii
发明人： Hiraku Chakihara , Yasushi Ishii
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L27/11573 , H01L29/42324 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.
摘要翻译：在半导体衬底的顶部上，形成了具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。在半导体衬底的顶部上，形成与层压图案相邻的存储栅电极。在控制栅极电极和半导体衬底之间形成第三绝缘膜用绝缘膜。在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成包括氧化硅膜，氮化硅膜和另一氧化硅膜的叠层膜的第四绝缘膜。在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

10. 发明授权

US08461642B2 Semiconductor device having a nonvolatile memory cell with field effect transistors 有权
标题翻译：具有具有场效应晶体管的非易失性存储单元的半导体器件
公开(公告)号：US08461642B2
公开(公告)日：2013-06-11
申请号：US12534140
申请日：2009-08-02
申请人： Takuro Homma , Yasushi Ishii , Kota Funayama
发明人： Takuro Homma , Yasushi Ishii , Kota Funayama
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11573 , H01L27/11 , H01L27/1104
摘要： The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.
摘要翻译：本发明可以实现具有配备有分离栅极结构的MONOS型非易失性存储单元的高度集成的半导体器件，而不会降低器件的可靠性。存储器nMIS的存储栅电极具有比选择nMIS的选择栅电极高20至100nm的高度，使得形成在一个侧面（源区侧面上的侧表面）的侧壁的宽度将存储栅电极的侧表面调节到实现所需干扰特性所需的宽度。此外，外围第二nMIS的栅电极具有不大于选择nMIS的选择栅电极的高度的高度，以减小形成在周边第二nMIS的栅电极的侧表面上的侧壁的宽度，所以防止共享的接触孔被侧壁填充。

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