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1. 发明申请

US20110095348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110095348A1
公开(公告)日：2011-04-28
申请号：US12913759
申请日：2010-10-27
申请人： Hiraku CHAKIHARA , Yasushi Ishii
发明人： Hiraku CHAKIHARA , Yasushi Ishii
IPC分类号： H01L29/94 , H01L21/336 , H01L27/088
CPC分类号： H01L27/11575 , H01L21/28273 , H01L21/28282 , H01L21/823443 , H01L21/823462 , H01L21/823835 , H01L27/0922 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11548 , H01L27/11565 , H01L27/11568 , H01L28/40 , H01L29/0649 , H01L29/42324 , H01L29/42328 , H01L29/4234 , H01L29/42344 , H01L29/4975 , H01L29/6653 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7881 , H01L29/792
摘要： Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.
摘要翻译：提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

2. 发明申请

US20130084684A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20130084684A1
公开(公告)日：2013-04-04
申请号：US13612630
申请日：2012-09-12
申请人： Yasushi ISHII , Hiraku CHAKIHARA , Takahiro MARUYAMA , Akihiro NAKAE
发明人： Yasushi ISHII , Hiraku CHAKIHARA , Takahiro MARUYAMA , Akihiro NAKAE
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/11573 , H01L28/60 , H01L29/42344 , H01L29/66833 , H01L29/792 , H01L2223/54426 , H01L2223/5446
摘要： The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.
摘要翻译：本发明提高了具有分裂栅极结构的非易失性存储单元的半导体器件的生产成本。存储垫的端部被覆盖的下层抗蚀剂膜的电平差为绅士，改善了形成在下层抗蚀剂膜上的抗蚀剂中间层的厚度的均匀性，并且防止了局部厚度减小或消失通过在形成在半导体衬底的存储单元区域中的每个选择栅极上形成氧化硅膜和氮化硅膜之后，在位于最外侧的选择栅电极上去除氧化硅膜和氮化硅膜（虚拟单元区域）。

3. 发明申请

US20090261390A1 SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090261390A1
公开(公告)日：2009-10-22
申请号：US12491756
申请日：2009-06-25
申请人： Masahiro MONIWA , Hiraku CHAKIHARA , Kousuke OKUYAMA , Yasuhiko TAKAHASHI
发明人： Masahiro MONIWA , Hiraku CHAKIHARA , Kousuke OKUYAMA , Yasuhiko TAKAHASHI
IPC分类号： H01L29/78 , H01L27/11
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的层压体，形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜和栅电极形成为覆盖层压体的侧壁。垂直MISFET是完全耗尽型MISFET。

4. 发明申请

US20100078705A1 NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE 有权
标题翻译：非易失性存储器半导体器件
公开(公告)号：US20100078705A1
公开(公告)日：2010-04-01
申请号：US12558502
申请日：2009-09-12
申请人： Hiraku CHAKIHARA , Tsutomo OKAZAKI
发明人： Hiraku CHAKIHARA , Tsutomo OKAZAKI
IPC分类号： H01L29/792
CPC分类号： H01L29/788 , H01L21/28282 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L29/42344 , H01L29/792
摘要： A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided.One end of an electricity supply line ESL is arranged over a terminal end TE1 and the other end thereof is arranged over a terminal end TE2, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end TE1, the terminal end TE2, and the dummy part DMY have substantially the same height, and therefore, most of the electricity supply line ESL arranged from over the terminal end TE1 to over the terminal end TE2 via the dummy part DMY is formed so as to have the same height.
摘要翻译：提供了一种能够提高非易失性存储器半导体器件的可靠性的技术，特别地，提供了一种能够不经过电源分配给分离栅晶体管的存储栅电极的技术。供电线ESL的一端设置在终端TE1的上端，其另一端配置在终端TE2的上方，而且供电线ESL的中心部分配置在虚拟部分DMY上。也就是说，终端TE1，终端TE2和虚拟部分DMY具有基本上相同的高度，因此，从终端TE1的上方排列的电力供给线ESL大部分经由虚拟的终端TE2 部分DMY形成为具有相同的高度。

5. 发明申请

US20110230041A1 SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 失效
标题翻译：半导体存储器件及其制造方法，制造垂直MISFET和垂直MISFET的方法以及制造半导体器件和半导体器件的方法
公开(公告)号：US20110230041A1
公开(公告)日：2011-09-22
申请号：US13150768
申请日：2011-06-01
申请人： Hiraku CHAKIHARA , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku CHAKIHARA , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L21/283
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
摘要翻译：垂直MISFET形成在驱动MISFET和传输MISFET上。垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极插入其间。在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。下半导体层，中间半导体层和上半导体层均由硅膜构成。下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

6. 发明申请

US20110129984A1 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20110129984A1
公开(公告)日：2011-06-02
申请号：US12956338
申请日：2010-11-30
申请人： Kota FUNAYAMA , Hiraku CHAKIHARA
发明人： Kota FUNAYAMA , Hiraku CHAKIHARA
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , G11C16/0425 , G11C16/0433 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L27/11565 , H01L27/11573 , H01L29/792
摘要： In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.
摘要翻译：在本发明中，在曝光于半导体存储器等的存储单元阵列等的光时，当用于蚀刻STI沟槽区域的一组单位开口，其中用于蚀刻每个STI沟槽区域的单位开口具有矩形形状的行和列通过曝光被转印到负的抗蚀剂膜上，适当地使用多次曝光，其包括使用具有在列方向上延伸的第一线性开口的组的第一光学掩模的第一曝光步骤，以及使用具有在行方向上延伸的一组第二线性开口的第二光学掩模的第二曝光步骤。

7. 发明申请

US20110121382A1 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110121382A1
公开(公告)日：2011-05-26
申请号：US12951012
申请日：2010-11-20
申请人： Hiraku CHAKIHARA , Yasuhi Ishii
发明人： Hiraku CHAKIHARA , Yasuhi Ishii
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L27/11573 , H01L29/42324 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.
摘要翻译：在半导体衬底的顶部上，形成了具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。在半导体衬底的顶部上，形成与层压图案相邻的存储栅电极。在控制栅极电极和半导体衬底之间形成第三绝缘膜用绝缘膜。在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成包括氧化硅膜，氮化硅膜和另一氧化硅膜的叠层膜的第四绝缘膜。在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

8. 发明申请

US20120129317A1 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20120129317A1
公开(公告)日：2012-05-24
申请号：US13365183
申请日：2012-02-02
申请人： Kota FUNAYAMA , Hiraku CHAKIHARA
发明人： Kota FUNAYAMA , Hiraku CHAKIHARA
IPC分类号： H01L21/8239
CPC分类号： H01L21/76229 , G11C16/0425 , G11C16/0433 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L27/11565 , H01L27/11573 , H01L29/792
摘要： In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.
摘要翻译：在本发明中，在曝光于半导体存储器等的存储单元阵列等的光时，当用于蚀刻STI沟槽区域的一组单位开口，其中用于蚀刻每个STI沟槽区域的单位开口具有矩形形状的行和列通过曝光被转印到负的抗蚀剂膜上，适当地使用多次曝光，其包括使用具有在列方向上延伸的第一线性开口的组的第一光学掩模的第一曝光步骤，以及使用具有在行方向上延伸的一组第二线性开口的第二光学掩模的第二曝光步骤。

9. 发明申请

US20090140342A1 SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体存储器件及其制造方法，制造垂直MISFET和垂直MISFET的方法以及制造半导体器件和半导体器件的方法
公开(公告)号：US20090140342A1
公开(公告)日：2009-06-04
申请号：US12364279
申请日：2009-02-02
申请人： Hiraku CHAKIHARA , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku CHAKIHARA , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L29/78
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
摘要翻译：垂直MISFET形成在驱动MISFET和传输MISFET上。垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极插入其间。在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。下半导体层，中间半导体层和上半导体层均由硅膜构成。下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

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