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1. 发明授权

US4860190A Computer system for controlling virtual machines 失效
标题翻译：用于控制虚拟机的计算机系统
公开(公告)号：US4860190A
公开(公告)日：1989-08-22
申请号：US902674
申请日：1986-09-02
申请人： Saburo Kaneda , Kazuaki Murakami
发明人： Saburo Kaneda , Kazuaki Murakami
IPC分类号： G06F9/46 , G06F13/10 , G06F13/24
CPC分类号： G06F13/24 , G06F13/10
摘要： A computer system for controlling virtual machines each given a different identification number. The system comprises mask registers and I/O interruption queues, each provided with the same numbers as the virtual machines, and corresponding to any one of the identification numbers. An interrupt handling in any one of the virtual machines can be carried out directly by using a pair of corresponding mask registers and I/O interruption queues without an interposition of the VM monitor.
摘要翻译：一种用于控制虚拟机的计算机系统，每个都具有不同的识别号码。该系统包括掩码寄存器和I / O中断队列，每个具有与虚拟机相同的号码，并且对应于任何一个标识号。可以通过使用一对相应的掩码寄存器和I / O中断队列直接执行任何一个虚拟机中的中断处理，而无需插入VM监视器。

2. 发明授权

US4400769A Virtual machine system 失效
标题翻译：虚拟机系统
公开(公告)号：US4400769A
公开(公告)日：1983-08-23
申请号：US198010
申请日：1980-10-21
申请人： Saburo Kaneda , Naomi Matsumura , Fujio Ikegami , Kazuyuki Shimizu , Yukichi Ikuta
发明人： Saburo Kaneda , Naomi Matsumura , Fujio Ikegami , Kazuyuki Shimizu , Yukichi Ikuta
IPC分类号： G06F9/46 , G06F9/455 , G06F9/48 , G06F12/10 , G06F9/00
CPC分类号： G06F9/4843 , G06F9/45533
摘要： A virtual machine system is provided with a control program for concurrently operating a plurality of OSs (Operating Systems). The object is to suppress the overhead produced when simulating privileged instructions for controlling program status words (PSWs). For this purpose, there is provided simple hardware, in place of the software control conventionally used, including a modification register for storing information required to modify the current PSW information and a pending register for storing pending interrupt information for communication to the corresponding OS.
摘要翻译： PCT No.PCT / JP80 / 00023 Sec。 371日期1980年10月21日 102（e）日期1980年10月15日PCT提交1980年2月20日PCT公布。出版物WO80 / 01850 日期为1980年9月4日。虚拟机系统具有用于同时操作多个OS（操作系统）的控制程序。目的是抑制模拟用于控制程序状态字（PSW）的特权指令时产生的开销。为此，提供简单的硬件，代替常规使用的软件控制，包括用于存储修改当前PSW信息所需的信息的修改寄存器和用于存储未决中断信息以用于通信给相应的操作系统的未决寄存器。

3. 发明授权

US4347565A Address control system for software simulation 失效
标题翻译：软件仿真地址控制系统
公开(公告)号：US4347565A
公开(公告)日：1982-08-31
申请号：US98989
申请日：1979-11-30
申请人： Saburo Kaneda , Takamitsu Tsuchimoto , Kazuyuki Shimizu , Fujio Ikegami
发明人： Saburo Kaneda , Takamitsu Tsuchimoto , Kazuyuki Shimizu , Fujio Ikegami
IPC分类号： G06F9/455 , G06F9/46 , G06F12/10 , G06F7/00 , G06F9/00
CPC分类号： G06F12/1036
摘要： An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.
摘要翻译：一种具有虚拟存储功能的虚拟机系统中用于软件仿真的地址控制系统。当模拟器程序模拟要仿真的程序的指令时，使用转换后备缓冲器实现要仿真的程序中的操作数地址的地址转换，从而大大减少了在模拟器程序执行期间的地址转换的开销。

4. 发明授权

US4057850A Processing link control device for a data processing system processing data by executing a main routine and a sub-routine 失效
标题翻译：处理链接控制装置，用于通过执行主程序和子程序来处理数据的数据处理系统
公开(公告)号：US4057850A
公开(公告)日：1977-11-08
申请号：US634401
申请日：1975-11-24
申请人： Saburo Kaneda , Koichi Tokura
发明人： Saburo Kaneda , Koichi Tokura
IPC分类号： B44F1/12 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/42 , G06F9/12 , G06F9/20
CPC分类号： G06F9/267
摘要： A data register storing an instruction code field, modification bits, a control bit field, condition branching fields and the next address in corresponding areas thereof is coupled to a control memory via a plurality of AND gates. A branch determination circuit for determining an instruction for selecting in accordance with a machine state, a single micro-instruction of four which are read out from the control memory, is connected to each AND gate for controlling them. The branch determination circuit is connected to the data register's condition branching field areas. A save-restore address register storing the address and branch address bits in corresponding areas thereof is coupled to the data register's next address area, the branch determination circuit, the control memory, from a first branch address bit area thereof to each AND gate for controlling them and is connected to a first bit modification control circuit. The second branch address bit area thereof is coupled to each AND gate for controlling them and is connected to a second bit modification control circuit. A save memory for storing the return address is coupled to the save-restore address register's address area and to the first and second bit modification control circuits. The save memory is coupled to the save-restore address register's address area whereby any of a plurality of return addresses is designated by selection of the modification bit in the branch and link instruction and access is provided simultaneously for four word address positions of the control memory by the next address, four micro-instructions are read out from the control memory by the next address and only one of the four micro-instructions is selected by the condition branching fields via the AND gates and set in the data register.
摘要翻译：存储指令代码字段，修改位，控制位字段，条件分支字段的数据寄存器和其对应区域中的下一个地址通过多个与门耦合到控制存储器。一个分支确定电路，用于根据机器状态确定用于选择的指令，从控制存储器读出的四个单个微指令连接到每个与门以进行控制。分支确定电路连接到数据寄存器的条件分支字段区域。存储其相应区域中的地址和分支地址位的保存还原地址寄存器被耦合到数据寄存器的下一个地址区域，分支确定电路，控制存储器，从其第一分支地址位区域到每个与门控制并连接到第一位修改控制电路。其第二分支地址位区域耦合到每个与门以进行控制，并连接到第二位修改控制电路。用于存储返回地址的保存存储器耦合到保存恢复地址寄存器的地址区域和第一和第二位修改控制电路。保存存储器耦合到保存还原地址寄存器的地址区域，由此通过选择分支中的修改位来指定多个返回地址中的任何一个，并且为控制存储器的四个字地址位置同时提供访问通过下一个地址，通过下一个地址从控制存储器中读出四个微指令，并且四个微指令中只有一个通过条件分支字段通过与门选择并设置在数据寄存器中。

5. 发明授权

US4027291A Access control unit 失效
标题翻译：门禁控制单元
公开(公告)号：US4027291A
公开(公告)日：1977-05-31
申请号：US610642
申请日：1975-09-05
申请人： Koichi Tokura , Saburo Kaneda
发明人： Koichi Tokura , Saburo Kaneda
IPC分类号： G06F9/28 , G02F1/1345 , G06F9/22 , G06F9/26 , G06F9/32 , G06F12/06 , G06F13/00
CPC分类号： G06F12/0607 , G06F9/267
摘要： An access control unit for controlling a memory device having a plurality of memory units for storing data in a manner whereby the memory units are accessed sequentially, comprises a data register for storing data read out from the memory device, a cycle designation device for indicating in every cycle the memory unit of the memory device to be accessed in the relevant cycle, an address device for providing in each cycle an address to the memory unit indicated by the cycle designation device, a non-coincidence detection circuit for detecting non-coincidence between the memory unit indicated by the address and the memory unit practically provided with that address, and an invalidating device utilizing the output of the non-coincidence detection circuit for invalidating data read out from the memory device in a cycle a specified number of cycles after that in which non-coincidence is detected.
摘要翻译：一种访问控制单元，用于控制具有多个存储单元的存储器件，所述存储器单元以按顺序存储存储器单元的方式存储数据，包括用于存储从存储器件读出的数据的数据寄存器，在相关周期中每个循环存储器件的存储器单元，一个地址装置，用于在每个周期中向由循环指定装置指示的存储器单元提供一个地址，一个不一致检测电路，用于检测由地址指示的存储器单元和实际上具有该地址的存储器单元，以及利用不符合检测电路的输出的无效设备，用于使从存储器件读出的数据在指定数量的周期之后的循环中无效其中检测不重合。

6. 发明授权

US4459661A Channel address control system for a virtual machine system 失效
标题翻译：用于虚拟机系统的通道地址控制系统
公开(公告)号：US4459661A
公开(公告)日：1984-07-10
申请号：US370193
申请日：1982-04-21
申请人： Saburo Kaneda , Masamichi Ishibashi , Yoshikatsu Seta , Fujio Ikegami
发明人： Saburo Kaneda , Masamichi Ishibashi , Yoshikatsu Seta , Fujio Ikegami
IPC分类号： G06F13/12 , G06F9/46 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F3/00
CPC分类号： G06F12/08
摘要： A virtual machine system having a virtual storage function, wherein registers are provided for holding the heading and trailing addresses of the continuous area in the main storage area assigned respectively for each of the plural operating systems. When the main storage area is accessed by a channel or sub-channel, one of the registers is selected, and the heading address of the register selected is added to the main storage address sent from the channel or sub-channel. The added main storage address is compared with the trailing address in the selected register and if the former is smaller than the latter, the overhead for supporting the virtual storage area is reduced by accessing the main storage area in accordance with the added main storage address mentioned above.
摘要翻译：一种具有虚拟存储功能的虚拟机系统，其特征在于，提供寄存器，用于将所述连续区域的标题和尾部地址保存在为多个操作系统中的每个操作系统分配的主存储区域中。当通过信道或子信道访问主存储区域时，选择其中一个寄存器，并且将所选择的寄存器的标题地址添加到从信道或子信道发送的主存储地址。将添加的主存储地址与所选寄存器中的尾部地址进行比较，如果前者小于后者，则通过根据添加的主存储地址访问主存储区域来减少用于支持虚拟存储区域的开销以上。

7. 发明授权

US4414620A Inter-subsystem communication system 失效
标题翻译：子系统间通信系统
公开(公告)号：US4414620A
公开(公告)日：1983-11-08
申请号：US204931
申请日：1980-11-07
申请人： Takamitsu Tsuchimoto , Saburo Kaneda , Tatsushi Miyazawa , Toshio Shimada , Hideo Suzuki , Mitsuru Sanagai , Kaoru Hiraoka
发明人： Takamitsu Tsuchimoto , Saburo Kaneda , Tatsushi Miyazawa , Toshio Shimada , Hideo Suzuki , Mitsuru Sanagai , Kaoru Hiraoka
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177 , G06F7/00 , G06F15/20
CPC分类号： G06F13/122 , G06F15/17
摘要： A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.
摘要翻译：在数据处理系统中实现高效数据传输的计算机系统之间的通信系统操作具有在独立或公共操作系统的控制下操作的发送器和接收器子系统。通信系统还包括：多个发送缓冲器，具有多个条目的发送缓冲器地址表和发送器子系统中的缓冲器控制块以及多个接收缓冲器，具有多个条目的接收缓冲器地址表和接收器子系统中的缓冲器控制块，以及用于将存储在发送缓冲器中的数据传送到接收缓冲器的通信路径。

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