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1. 发明授权

US09933553B2 Optical element and optical device 有权
公开(公告)号：US09933553B2
公开(公告)日：2018-04-03
申请号：US14403684
申请日：2012-06-21
申请人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
发明人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
IPC分类号： G02F1/1335 , G02B5/30 , G03B21/20 , G03B21/00
CPC分类号： G02B5/3058 , G02F1/133536 , G02F2001/133548 , G03B21/006 , G03B21/2073
摘要： Provided are an optical element and an optical device using the optical element to which a manufacturing process for manufacturing a wire-grid structure can be basically applied, and besides, in which a higher polarization contrast ratio than that of a wire-grid element can be obtained. A wobbled wire element in an embodiment has a feature that a periodic structure having a period equal to or larger than a wavelength of an incident light wave is formed in a y direction. In this manner, in a wobbled wire element in a first embodiment, a polarization contrast ratio can be significantly improved.

2. 发明授权

US10310321B2 Optical element, manufacturing method of optical element, and optical device 有权
公开(公告)号：US10310321B2
公开(公告)日：2019-06-04
申请号：US14404529
申请日：2012-06-21
申请人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
发明人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
IPC分类号： G02F1/1335 , G02B5/30 , G03B21/20 , G03B33/12 , H04N9/31 , G02F1/1333
摘要： In order to improve a characteristic of an optical element, an optical element (polarizing filter) including a substrate 1S having a wire-grid region 1A and a peripheral region 2A positioned on an outer periphery thereof is made to have the following configuration. A wire-grid in which a plurality of line-shaped wires P10 made of Al and extending in a y direction are arranged at spaces S in an x direction is provided in the wire-grid region 1A of the substrate 1S, and a pattern (repetitive pattern) in which a plurality of protruding portions P20 made of Al are arranged is provided in the peripheral region 2A. This pattern is, for example, a checkerboard pattern. According to the above-mentioned configuration, the plurality of wires P10 can be arranged so that their respective ends are spaced apart from an end of the substrate 1S, so that the wires P10 can be prevented from being deformed and nicked. Also, by the plurality of protruding portions P20 in the peripheral region 2A, it is possible to prevent water from entering the wire-grid region 1A.

3. 发明申请

US20150234230A1 OPTICAL ELEMENT, MANUFACTURING METHOD OF OPTICAL ELEMENT, AND OPTICAL DEVICE 审中-公开
标题翻译：光学元件，光学元件的制造方法和光学器件
公开(公告)号：US20150234230A1
公开(公告)日：2015-08-20
申请号：US14404529
申请日：2012-06-21
申请人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
发明人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
IPC分类号： G02F1/1335 , G02B5/30
CPC分类号： G02F1/133528 , G02B5/30 , G02B5/3058 , G02F2001/133548 , G03B21/2073 , G03B33/12 , H04N9/3105 , H04N9/3167
摘要： In order to improve a characteristic of an optical element, an optical element (polarizing filter) including a substrate 1S having a wire-grid region 1A and a peripheral region 2A positioned on an outer periphery thereof is made to have the following configuration. A wire-grid in which a plurality of line-shaped wires P10 made of Al and extending in a y direction are arranged at spaces S in an x direction is provided in the wire-grid region 1A of the substrate 1S, and a pattern (repetitive pattern) in which a plurality of protruding portions P20 made of Al are arranged is provided in the peripheral region 2A. This pattern is, for example, a checkerboard pattern. According to the above-mentioned configuration, the plurality of wires P10 can be arranged so that their respective ends are spaced apart from an end of the substrate 1S, so that the wires P10 can be prevented from being deformed and nicked. Also, by the plurality of protruding portions P20 in the peripheral region 2A, it is possible to prevent water from entering the wire-grid region 1A.
摘要翻译：为了提高光学元件的特性，使具有线栅区域1A的基板1S和位于其外周的周边区域2A的光学元件（偏振滤光器）具有以下结构。在基板1S的线栅区域1A中设置有线状，其中由Al构成的多条线状导线P10沿y方向布置在x方向的间隔S处，并且形成图案（重复图案），其中布置有多个由Al制成的突出部分P20设置在周边区域2A中。该模式例如是棋盘图案。根据上述结构，可以将多根电线P10配置成使它们各自的端部与基板1S的一端分开，从而可以防止电线P10变形和断开。此外，通过周边区域2A中的多个突出部P20，可以防止水进入线栅区域1A。

4. 发明申请

US20150226896A1 OPTICAL ELEMENT AND OPTICAL DEVICE 有权
标题翻译：光学元件和光学器件
公开(公告)号：US20150226896A1
公开(公告)日：2015-08-13
申请号：US14403684
申请日：2012-06-21
申请人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
发明人： Koji Hirata , Hiroyuki Minemura , Yumiko Anzai , Tetsuya Nishida , Jiro Yamamoto , Naoyuki Kofuji , Hidehiro Ikeda , Nobuyuki Kimura
IPC分类号： G02B5/30 , G03B21/20 , G03B21/00
CPC分类号： G02B5/3058 , G02F1/133536 , G02F2001/133548 , G03B21/006 , G03B21/2073
摘要： Provided are an optical element and an optical device using the optical element to which a manufacturing process for manufacturing a wire-grid structure can be basically applied, and besides, in which a higher polarization contrast ratio than that of a wire-grid element can be obtained. A wobbled wire element in an embodiment has a feature that a periodic structure having a period equal to or larger than a wavelength of an incident light wave is formed in a y direction. In this manner, in a wobbled wire element in a first embodiment, a polarization contrast ratio can be significantly improved.
摘要翻译：提供一种光学元件和使用能够基本上应用制造线栅结构的制造工艺的光学元件的光学元件，此外，与线栅元件相比，具有更高的偏振对比度可以是获得。一个实施例中的摆动线元件具有在y方向上形成具有等于或大于入射光波长的周期的周期性结构的特征。以这种方式，在第一实施例的摆动线元件中，可以显着提高偏振对比度。

5. 发明授权

US08129283B2 Plasma processing method and plasma processing apparatus 有权
标题翻译：等离子体处理方法和等离子体处理装置
公开(公告)号：US08129283B2
公开(公告)日：2012-03-06
申请号：US12068889
申请日：2008-02-13
申请人： Masahito Mori , Naoyuki Kofuji , Naoshi Itabashi
发明人： Masahito Mori , Naoyuki Kofuji , Naoshi Itabashi
IPC分类号： H01L21/302
CPC分类号： H01J37/32798 , C23F4/00 , H01J37/32009 , H01J37/32183 , H01J37/32706 , H01L21/31116 , H01L21/31138 , H01L21/32136 , H01L21/32137 , H01L29/517
摘要： The invention provides a plasma processing apparatus and a dry etching method for etching a multilayered film structure having steps with high accuracy. The plasma processing apparatus comprises a vacuum reactor 107, a lower electrode 113 placed within a processing chamber of the vacuum reactor and having a wafer 112 to be etched mounted on the upper surface thereof, bias supplying units 118 and 120 for supplying high frequency power for forming a bias potential to the lower electrode 113, a gas supply means 111 for feeding reactive gas into the processing chamber, an electric field supplying means 101 through 103 for supplying a magnetic field for generating plasma in the processing chamber, and a control unit 127 for controlling the distribution of ion energy in the plasma being incident on the wafer 112 via the high frequency power.
摘要翻译：本发明提供一种用于蚀刻具有高精度步骤的多层膜结构的等离子体处理装置和干蚀刻方法。等离子体处理装置包括真空反应器107，放置在真空反应器的处理室内的下部电极113，并且具有要在其上表面上安装的晶片112的偏压供给单元118和120，用于向向下电极113形成偏置电位，用于将反应性气体供给到处理室中的气体供给装置111，用于在处理室中提供用于产生等离子体的磁场的电场供给装置101至103，以及控制单元127 用于控制通过高频功率入射在晶片112上的等离子体中的离子能量的分布。

6. 发明申请

US20080190893A1 Plasma processing method and plasma processing apparatus 有权
标题翻译：等离子体处理方法和等离子体处理装置
公开(公告)号：US20080190893A1
公开(公告)日：2008-08-14
申请号：US12068889
申请日：2008-02-13
申请人： Masahito Mori , Naoyuki Kofuji , Naoshi Itabashi
发明人： Masahito Mori , Naoyuki Kofuji , Naoshi Itabashi
IPC分类号： C23F1/00 , C23F1/08
CPC分类号： H01J37/32798 , C23F4/00 , H01J37/32009 , H01J37/32183 , H01J37/32706 , H01L21/31116 , H01L21/31138 , H01L21/32136 , H01L21/32137 , H01L29/517
摘要： The invention provides a plasma processing apparatus and a dry etching method for etching a multilayered film structure having steps with high accuracy. The plasma processing apparatus comprises a vacuum reactor 107, a lower electrode 113 placed within a processing chamber of the vacuum reactor and having a wafer 112 to be etched mounted on the upper surface thereof, bias supplying units 118 and 120 for supplying high frequency power for forming a bias potential to the lower electrode 113, a gas supply means 111 for feeding reactive gas into the processing chamber, an electric field supplying means 101 through 103 for supplying a magnetic field for generating plasma in the processing chamber, and a control unit 127 for controlling the distribution of ion energy in the plasma being incident on the wafer 112 via the high frequency power.
摘要翻译：本发明提供一种用于蚀刻具有高精度步骤的多层膜结构的等离子体处理装置和干蚀刻方法。等离子体处理装置包括真空反应器107，放置在真空反应器的处理室内的下部电极113，并且具有要在其上表面上安装的晶片112的偏压供给单元118和120，用于向向下电极113形成偏置电位，用于将反应性气体供给到处理室中的气体供给装置111，用于在处理室中提供用于产生等离子体的磁场的电场供给装置101至103，以及控制单元127 用于控制通过高频功率入射在晶片112上的等离子体中的离子能量的分布。

7. 发明申请

US20070199657A1 Apparatus and method for plasma etching 审中-公开
标题翻译：用于等离子体蚀刻的装置和方法
公开(公告)号：US20070199657A1
公开(公告)日：2007-08-30
申请号：US11500360
申请日：2006-08-08
申请人： Naoyuki Kofuji , Hiroshi Akiyama
发明人： Naoyuki Kofuji , Hiroshi Akiyama
IPC分类号： H01L21/306 , C23F1/00
CPC分类号： H01L21/32137 , H01J37/3244 , H01J37/32935
摘要： The invention aims at solving the problems of throughput deterioration, reproducibility deterioration and plasma discharge instability when performing continuous discharge during multiple steps of plasma etching. According to the present invention, the gas supply unit is operated while determining the timing for switching conditions of a plurality of plasma etching steps, and the gas flow rate and gas pressure are controlled so that the pressure of processing gas supplied from the gas supply unit to the processing chamber does not fall below a predetermined pressure immediately subsequent to switching steps. For example, upon switching processing gases, the end point of a step is predicted based on an interference film thickness meter, and prior to the end point by two seconds or more, the flow rate of MFC is set to the gas flow rate for the subsequent step and the gas is flown to the exhaust device, so that simultaneously as when the end point signal is received, the processing gases are switched by switching valves.
摘要翻译：本发明旨在解决在等离子体蚀刻的多个步骤期间执行连续放电时的吞吐量劣化，再现性劣化和等离子体放电不稳定性的问题。根据本发明，在确定多个等离子体蚀刻步骤的切换条件的定时的同时操作气体供给单元，并且控制气体流量和气体压力，使得从气体供应单元供应的处理气体的压力到切换步骤之后，处理室不会下降到预定压力以下。例如，在切换处理气体时，基于干涉膜厚度计预测台阶的终点，并且在终点2秒以上之前，将MFC的流量设定为随后的步骤和气体流到排气装置，从而同时当接收到终点信号时，处理气体由切换阀切换。

8. 发明申请

US20110253672A1 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD 审中-公开
标题翻译：等离子体加工设备和等离子体处理方法
公开(公告)号：US20110253672A1
公开(公告)日：2011-10-20
申请号：US12855206
申请日：2010-08-12
申请人： Masami Kamibayashi , Masahito Mori , Hiroyuki Kobayashi , Keizo Suzuki , Naoyuki Kofuji
发明人： Masami Kamibayashi , Masahito Mori , Hiroyuki Kobayashi , Keizo Suzuki , Naoyuki Kofuji
IPC分类号： C23F1/12 , H01L21/306 , C23F1/08
CPC分类号： H01J37/32678 , H01J37/32091 , H01L21/32136
摘要： The present invention is intended to improve the uniformity in a distribution function of incident ion energy inside a wafer surface, and realize uniform plasma processing (etching or the like) inside the wafer surface. In a plasma processing apparatus, a bias application portion of a placement electrode on which a wafer is placed is divided into an inner electrode and an outer electrode at positions near the center of the wafer and the edge thereof. Each of a first bias power and a second bias power to be used to accelerate ions incident on the wafer is bifurcated, and the resultant bias powers are fed to the inner electrode and outer electrode using a power distributor by adjusting the power ratio.
摘要翻译：本发明旨在提高晶片表面内的入射离子能的分布函数的均匀性，并且在晶片表面内实现均匀的等离子体处理（蚀刻等）。在等离子体处理装置中，放置晶片的放置电极的偏置施加部分在晶片的中心和边缘附近的位置被分成内电极和外电极。用于加速入射在晶片上的离子的第一偏置功率和第二偏置功率分别被分叉，并且通过调节功率比，使用功率分配器将所得到的偏置功率馈送到内部电极和外部电极。

9. 发明申请

US20060076315A1 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus 有权
公开(公告)号：US20060076315A1
公开(公告)日：2006-04-13
申请号：US11242905
申请日：2005-10-05
申请人： Naoyuki Kofuji
发明人： Naoyuki Kofuji
IPC分类号： G01L21/30 , C23F1/00
CPC分类号： H01J37/32963 , H01J37/32935 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer.

10. 发明申请

US20050227470A1 Method for manufacturing a semiconductor device having a W/WN/polysilicon layered film 有权
标题翻译：具有W / WN /多晶硅层状膜的半导体器件的制造方法
公开(公告)号：US20050227470A1
公开(公告)日：2005-10-13
申请号：US11099609
申请日：2005-04-06
申请人： Naoyuki Kofuji
发明人： Naoyuki Kofuji
IPC分类号： H01L21/3065 , C23F4/00 , H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/3213 , H01L21/4763 , H01L23/52 , H01L29/49 , H01L29/78
CPC分类号： H01L21/02071 , H01L21/28061 , H01L21/32136 , H01L29/4941
摘要： A method for manufacturing a semiconductor device includes the steps of consecutively depositing a Poly-Si layer, a WN layer and a W layer on a SiO2 layer, forming a mask pattern on the W layer, selectively etching the W layer by using plasma in a first etching gas having a high etch selectivity ratio between W and WN, selectively etching the WN layer and the Poly-Si layer by using plasma in a second etching gas having a high etch selectivity between WN and Si, and selectively etching the Poly-Si layer 13 by using plasma in a third etching gas having a high etch selectivity between Si and silicon oxide.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在SiO 2层上连续沉积多晶硅层，WN层和W层，在W层上形成掩模图案，选择性蚀刻通过在W和WN之间具有高蚀刻选择性比的第一蚀刻气体中使用等离子体，通过在WN和Si之间具有高蚀刻选择性的第二蚀刻气体中使用等离子体来选择性地蚀刻WN层和多晶硅层并且通过在Si和氧化硅之间具有高蚀刻选择性的第三蚀刻气体中使用等离子体来选择性地蚀刻多晶硅层13。

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