专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140035618A1 CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING 有权
标题翻译：具有可编程匹配确定功能的电路，以及具有这种功能的LUT电路，多路复用电路和FPGA器件以及数据写入方法
公开(公告)号：US20140035618A1
公开(公告)日：2014-02-06
申请号：US13613701
申请日：2012-09-13
申请人： Kosuke TATSUMURA , Masato ODA , Atsuhiro KINOSHITA , Koichiro ZAITSU , Mari MATSUMOTO , Shinichi YASUDA
发明人： Kosuke TATSUMURA , Masato ODA , Atsuhiro KINOSHITA , Koichiro ZAITSU , Mari MATSUMOTO , Shinichi YASUDA
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G11C15/04 , G11C15/046 , H03K19/17712
摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.
摘要翻译：根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

2. 发明申请

US20130241596A1 PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：可编程逻辑器件
公开(公告)号：US20130241596A1
公开(公告)日：2013-09-19
申请号：US13605646
申请日：2012-09-06
申请人： Mari MATSUMOTO , Kosuke Tatsumura , Koichiro Zaitsu
发明人： Mari MATSUMOTO , Kosuke Tatsumura , Koichiro Zaitsu
IPC分类号： H03K19/094
CPC分类号： G11C16/0441 , G11C16/3418 , H03K19/1776
摘要： One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire.
摘要翻译：一个实施例提供了一种可编程逻辑器件，其中逻辑开关包括：第一存储器，其具有连接到第一线的第一端子，连接到第二线的第二端子和连接到第三线的第三端子; 第二存储器，具有连接到第一线的第四端子，连接到第四线的第五端子和连接到第五线的第六端子; 以及具有连接到第一端子的栅极的通过晶体管，以及分别连接到第六线和第七线的源极和漏极。第一选择栅极晶体管的源极或漏极连接第六导线，第二选择栅极晶体管的源极或漏极连接到第七导线。

3. 发明申请

US20150014748A1 SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路，可编程逻辑器件，制造半导体集成电路的方法
公开(公告)号：US20150014748A1
公开(公告)日：2015-01-15
申请号：US14500349
申请日：2014-09-29
申请人： Koichiro ZAITSU , Kosuke TATSUMURA , Mari MATSUMOTO
发明人： Koichiro ZAITSU , Kosuke TATSUMURA , Mari MATSUMOTO
IPC分类号： H01L27/118
CPC分类号： H01L27/11803 , G11C16/04 , G11C16/0441 , G11C16/10 , H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L27/11573 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H03K19/17764 , H03K19/17792
摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
摘要翻译：根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

4. 发明申请

US20130258782A1 CONFIGURATION MEMORY 有权
标题翻译：配置存储器
公开(公告)号：US20130258782A1
公开(公告)日：2013-10-03
申请号：US13603666
申请日：2012-09-05
申请人： Kosuke TATSUMURA , Masato ODA , Koichiro ZAITSU , Atsushi KAWASUMI , Mari MATSUMOTO , Shinichi YASUDA
发明人： Kosuke TATSUMURA , Masato ODA , Koichiro ZAITSU , Atsushi KAWASUMI , Mari MATSUMOTO , Shinichi YASUDA
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C7/06 , G11C16/26
摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.
摘要翻译：根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路配置数据输出节点。

5. 发明申请

US20120089656A1 RANDOM NUMBER GENERATOR CIRCUIT AND CRYPTOGRAPHIC CIRCUIT 有权
标题翻译：随机数发生器电路和编码电路
公开(公告)号：US20120089656A1
公开(公告)日：2012-04-12
申请号：US13301932
申请日：2011-11-22
申请人： Tetsufumi TANAMOTO , Mari MATSUMOTO , Shinobu FUJITA , Kazutaka IKEGAMI
发明人： Tetsufumi TANAMOTO , Mari MATSUMOTO , Shinobu FUJITA , Kazutaka IKEGAMI
IPC分类号： G06F7/58
CPC分类号： H03K3/84 , G06F7/58
摘要： A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.
摘要翻译：随机数生成电路包括：生成并输出物理随机数的元素; 数字化电路将物理随机数字化，以输出由测试电路测试的随机数序列; 以及纠错码电路，包括具有输入的随机数序列的移位寄存器，将所存储的随机数序列乘以纠错码生成矩阵的乘法器和输出移位寄存器的输出和根据由测试电路获得的测试结果的乘数的输出。当由测试电路执行的测试结果指示拒绝时，纠错码电路将来自选择器开关的乘法器的输出作为校正的随机数序列输出。当测试结果表明拒绝时，测试电路测试校正的随机数序列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式