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1. 发明申请

US20120089656A1 RANDOM NUMBER GENERATOR CIRCUIT AND CRYPTOGRAPHIC CIRCUIT 有权
标题翻译：随机数发生器电路和编码电路
公开(公告)号：US20120089656A1
公开(公告)日：2012-04-12
申请号：US13301932
申请日：2011-11-22
申请人： Tetsufumi TANAMOTO , Mari MATSUMOTO , Shinobu FUJITA , Kazutaka IKEGAMI
发明人： Tetsufumi TANAMOTO , Mari MATSUMOTO , Shinobu FUJITA , Kazutaka IKEGAMI
IPC分类号： G06F7/58
CPC分类号： H03K3/84 , G06F7/58
摘要： A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.
摘要翻译：随机数生成电路包括：生成并输出物理随机数的元素; 数字化电路将物理随机数字化，以输出由测试电路测试的随机数序列; 以及纠错码电路，包括具有输入的随机数序列的移位寄存器，将所存储的随机数序列乘以纠错码生成矩阵的乘法器和输出移位寄存器的输出和根据由测试电路获得的测试结果的乘数的输出。当由测试电路执行的测试结果指示拒绝时，纠错码电路将来自选择器开关的乘法器的输出作为校正的随机数序列输出。当测试结果表明拒绝时，测试电路测试校正的随机数序列。

2. 发明申请

US20100073025A1 PROGRAMMABLE LOGIC CIRCUIT 有权
标题翻译：可编程逻辑电路
公开(公告)号：US20100073025A1
公开(公告)日：2010-03-25
申请号：US12404606
申请日：2009-03-16
申请人： Tetsufumi TANAMOTO , Hideyuki SUGIYAMA , Kazutaka IKEGAMI , Yoshiaki SAITO
发明人： Tetsufumi TANAMOTO , Hideyuki SUGIYAMA , Kazutaka IKEGAMI , Yoshiaki SAITO
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C13/0002 , H03K19/17764 , H03K19/1778 , H03K19/17784 , H03K19/18
摘要： A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.
摘要翻译：可编程逻辑电路包括：输入电路，被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列，每个单元可编程单元包括电阻改变型的第一存储器电路，包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路并联连接的第一和第二存储器电路，同一行上的第一晶体管的每个栅极分别接收一个输入信号，同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号，第一个输出端的输出端并且同一列上的第二存储器电路连接到公共输出线。

3. 发明申请

US20130268795A1 CACHE SYSTEM AND INFORMATION-PROCESSING DEVICE 有权
标题翻译：缓存系统和信息处理设备
公开(公告)号：US20130268795A1
公开(公告)日：2013-10-10
申请号：US13729382
申请日：2012-12-28
申请人： Kumiko NOMURA , Shinobu FUJITA , Keiko ABE , Kazutaka IKEGAMI , Hiroki NOGUCHI
发明人： Kumiko NOMURA , Shinobu FUJITA , Keiko ABE , Kazutaka IKEGAMI , Hiroki NOGUCHI
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.
摘要翻译：根据一个实施例，缓存系统包括标签存储器，其包括易失性存储器设备，标签存储器包括每条线路的方式和存储标签，数据存储器包括包括用于读取数据的读出放大器的非易失性存储器件，数据存储器包括方式和存储每行的数据，比较电路，被配置为将从外部提供的地址中包含的标签与从标签存储器读取的标签进行比较，以及控制器，被配置为关闭读出放大器的功率，基于比较电路的比较结果不被访问。

4. 发明申请

US20090177725A1 RANDOM NUMBER GENERATION DEVICE 有权
标题翻译：随机数生成装置
公开(公告)号：US20090177725A1
公开(公告)日：2009-07-09
申请号：US12212205
申请日：2008-09-17
申请人： Kazutaka IKEGAMI , Shinichi Yasuda
发明人： Kazutaka IKEGAMI , Shinichi Yasuda
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured to receive an output of the current noise source; and a conversion circuit configured to convert output frequency fluctuation of the ring oscillator to a random number and output the random number.
摘要翻译：可以提供尽可能少的功率消耗来生成物理随机数的随机数生成装置。随机数生成装置包括：环形振荡器，其具有至少一组，每组包括电流噪声源，施密特反相器被配置为接收当前噪声源的输出; 以及转换电路，被配置为将环形振荡器的输出频率波动转换为随机数，并输出随机数。

5. 发明申请

US20120221616A1 RANDOM NUMBER GENERATION CIRCUIT 有权
标题翻译：随机数生成电路
公开(公告)号：US20120221616A1
公开(公告)日：2012-08-30
申请号：US13428150
申请日：2012-03-23
申请人： Shinichi YASUDA , Kazutaka IKEGAMI
发明人： Shinichi YASUDA , Kazutaka IKEGAMI
IPC分类号： G06F7/58
CPC分类号： H03K3/84 , G06F7/588
摘要： According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.
摘要翻译：根据一个实施例，随机数生成电路包括振荡电路和保持电路。振荡电路具有放大器阵列和高噪声电路。放大器在放大器阵列中串联连接，放大器阵列在相邻放大器之间具有一个端子。高噪声电路插入在放大器阵列中的其它相邻放大器之间，高噪声电路产生在放大器阵列的振荡信号中产生抖动所需的噪声。保持电路作为随机数输出根据时钟信号保持的振荡信号。

6. 发明申请

US20090222502A1 RANDOM NUMBER GENERATOR 有权
标题翻译：随机数发电机
公开(公告)号：US20090222502A1
公开(公告)日：2009-09-03
申请号：US12235995
申请日：2008-09-23
申请人： Kazutaka IKEGAMI , Shinichi Yasuda
发明人： Kazutaka IKEGAMI , Shinichi Yasuda
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.
摘要翻译：随机数发生器包括：可变频率振荡器，包括：具有多个输入端子和输出端子的选择电路; 并联电路，其具有分别连接到选择电路的输入端子的输入端子和多个输出端子，并联电路包括由选择电路选择的一个或多个缓冲电路; 以及具有控制端子的逆变器电路，所述逆变器电路连接到所述并联电路的输入端子和所述选择电路的输出端子; 以及连接到可变频率振荡器的锁存电路。

7. 发明申请

US20120080739A1 NONVOLATILE PROGRAMMABLE LOGIC SWITCH 失效
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US20120080739A1
公开(公告)日：2012-04-05
申请号：US13221292
申请日：2011-08-30
申请人： Daisuke HAGISHIMA , Atsuhiro KINOSHITA , Kazuya MATSUZAWA , Kazutaka IKEGAMI , Yoshifumi NISHI
发明人： Daisuke HAGISHIMA , Atsuhiro KINOSHITA , Kazuya MATSUZAWA , Kazutaka IKEGAMI , Yoshifumi NISHI
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/1052 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L29/66825
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

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