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1. 发明授权

US06925028B2 DRAM with multiple virtual bank architecture for random row access 失效
标题翻译：具有多个虚拟银行架构的DRAM用于随机行访问
公开(公告)号：US06925028B2
公开(公告)日：2005-08-02
申请号：US10473632
申请日：2002-03-06
申请人： Kohji Hosokawa , Toshio Sunaga , Shinpei Watanabe
发明人： Kohji Hosokawa , Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C11/401 , G11C11/407 , G11C11/408 , G11C11/4097 , G11C8/00
CPC分类号： G11C7/1066 , G11C11/408 , G11C11/4087 , G11C11/4097
摘要： A DRAM and access method for DRAM with a high data rate in a random row access mode. The DRAM includes a plurality of memory blocks composed of a plurality of storage segments each with a series of main word lines and sub-word lines. Each memory block is decoded into multiple segments and the main word lines are activated to select a predetermined number of sub-word lines. A corner block is provided that contains a plurality of Z-lines for selecting one of the sub-wordlines and a plurality of segment select lines for selecting a specific memory segment by activating a local Z-line.
摘要翻译：一种具有随机行访问模式的高数据速率的DRAM的DRAM和存取方法。 DRAM包括由多个存储段组成的多个存储块，每个存储段具有一系列主字线和子字线。每个存储块被解码成多个段，并且主字线被激活以选择预定数量的子字线。提供了一个角块，其包含用于选择子字线之一的多条Z线和用于通过激活本地Z线来选择特定存储器段的多个段选择线。

2. 发明申请

US20060250873A1 Dynamic semiconductor storage device 失效
标题翻译：动态半导体存储设备
公开(公告)号：US20060250873A1
公开(公告)日：2006-11-09
申请号：US10553578
申请日：2004-04-13
申请人： Kohji Hosokawa , Hisatada Miyatake , Toshio Sunaga
发明人： Kohji Hosokawa , Hisatada Miyatake , Toshio Sunaga
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.
摘要翻译：为了通过简单的电路配置来实现通过选择性地设置刷新周期来有效地降低刷新电流的DRAM。存储单元阵列被分成64个子阵列，每个子阵列进一步分成8个块。刷新周期控制电路具有用于设定分频比为1或1/2的熔丝电路，分频器，其将预解码信号的频率除以设定的分频比，用于设定分频比为1的熔丝电路或1/4，以及用于将预解码信号除以设定分频比的分频器。刷新周期控制电路能够为64个子阵列设置64 ms或128 ms的刷新周期，512个块的64 ms或256 ms刷新周期。

3. 发明授权

US07313045B2 Dynamic semiconductor storage device 失效
标题翻译：动态半导体存储设备
公开(公告)号：US07313045B2
公开(公告)日：2007-12-25
申请号：US10553578
申请日：2004-04-13
申请人： Kohji Hosokawa , Hisatada Miyatake , Toshio Sunaga
发明人： Kohji Hosokawa , Hisatada Miyatake , Toshio Sunaga
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.
摘要翻译：为了通过简单的电路配置来实现通过选择性地设置刷新周期来有效地降低刷新电流的DRAM。存储单元阵列被分成64个子阵列，每个子阵列进一步分成8个块。刷新周期控制电路具有用于设定分频比为1或1/2的熔丝电路，分频器，其将预解码信号的频率除以设定的分频比，用于设定分频比为1的熔丝电路或1/4，以及用于将预解码信号除以设定分频比的分频器。刷新周期控制电路能够为64个子阵列设置64 ms或128 ms的刷新周期，512个块的64 ms或256 ms刷新周期。

4. 发明申请

US20080291746A1 Semiconductor Storage Device and Burst Operation Method 审中-公开
标题翻译：半导体存储设备和突发操作方法
公开(公告)号：US20080291746A1
公开(公告)日：2008-11-27
申请号：US10595742
申请日：2004-11-04
申请人： Toshio Sunaga , Kohji Hosokawa , Hisatada Miyatake , Yutaka Nakamura
发明人： Toshio Sunaga , Kohji Hosokawa , Hisatada Miyatake , Yutaka Nakamura
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4076 , G11C7/08 , G11C7/1018 , G11C11/4096
摘要： The present invention is a PSRAM in which a burst length can be increased without increasing consumed current, and a burst operation method therefor. In operation, column selection lines CSL1 and CSL2 are driven in order during activation of sense amplifiers. This causes bit switches BSW1-BSW8 to be turned on in units of four bit switches and then 8-bit read data RD is latched from bit line pairs BL1-BL8 into prefetch/preload latches PFPLL1-PFPLL8 in units of 4-bits. The 8-bit read data RD is continuously output to a single data I/O bus I/O1 in units of one bit and in order.
摘要翻译：本发明是一种PSRAM，其中可以增加突发长度而不增加消耗电流，以及其突发操作方法。在操作中，列选择线CSL1和CSL2在感测放大器的激活期间按顺序驱动。这使得位开关BSW1-BSW8以四位开关为单位接通，然后8位读数据RD从位线对BL1-BL8以4位为单位锁存到预取/预加载锁存器PFPLL1-PFPLL8中。 8位读数据RD以1位为单位连续输出到单个数据I / O总线I / O1。

5. 发明授权

US06252810B1 Circuit and method for detecting defects in semiconductor memory 失效
标题翻译：用于检测半导体存储器中的缺陷的电路和方法
公开(公告)号：US06252810B1
公开(公告)日：2001-06-26
申请号：US09636477
申请日：2000-08-10
申请人： Kohji Hosokawa
发明人： Kohji Hosokawa
IPC分类号： G11C818
CPC分类号： G11C29/84 , G11C29/44
摘要： A defect detecting circuit of the present invention accelerates comparison and judgment by making an address-information renewing and holding circuit 2′ previously hold outputs (program information) of a program-information holding circuit 1′ at the end of the last operation as address information before renewing and holding addresses in the address-information renewing and holding circuit 2′ and thereby simplifying a configuration of a compare and detection Circuit 3′.
摘要翻译：本发明的缺陷检测电路通过使地址信息更新保持电路2'预先在最后一次操作结束时保存节目信息保持电路1'的输出（节目信息）来加速比较和判断，作为地址信息在地址信息更新保持电路2'中更新并保持地址之前，从而简化比较和检测电路3'的配置。

6. 发明授权

US06452832B2 DRAM circuit and method of controlling the same 有权
标题翻译： DRAM电路及其控制方法
公开(公告)号：US06452832B2
公开(公告)日：2002-09-17
申请号：US09681200
申请日：2001-02-19
申请人： Kohji Hosokawa
发明人： Kohji Hosokawa
IPC分类号： G11C1124
CPC分类号： G11C7/1006 , G11C7/1048
摘要： To provide a DRAM circuit capable of achieving a high speed write operation even when the write operation is accompanied with a write masking operation, and a method of controlling the same. A DRAM circuit of the present invention has a novel column switch for connecting a bit line pair and a data line pair via a sense amplifier. The novel column switch has a function to separate a bit line pair corresponding to a selected data line pair during the write mask operation. As a result, even if the column switch is made to be ON before the it line pair is sufficiently amplified by the sense amplifier, there is no fear that data on the bit line pair is destroyed due to a malfunction of the sense amplifier, thus making it possible to achieve a high speed write operation without depending on whether the write masking operation in the DRAM circuit is performed or not.
摘要翻译：为了提供即使在写入操作伴随写入屏蔽操作时也能够实现高速写入操作的DRAM电路及其控制方法。本发明的DRAM电路具有用于经由读出放大器连接位线对和数据线对的新颖的列开关。该新颖的列开关具有在写掩模操作期间分离与所选数据线对对应的位线对的功能。结果，即使在线对被感测放大器充分放大之前使列开关变为ON，也不必担心位线对上的数据由于读出放大器的故障而被破坏，因此使得可以实现高速写入操作，而不依赖于是否执行DRAM电路中的写入屏蔽操作。

7. 发明授权

US6002275A Single ended read write drive for memory 失效
标题翻译：用于内存的单端读写驱动器
公开(公告)号：US6002275A
公开(公告)日：1999-12-14
申请号：US17015
申请日：1998-02-02
申请人： Kohji Hosokawa , Toshiaki Kirihata
发明人： Kohji Hosokawa , Toshiaki Kirihata
IPC分类号： G11C11/409 , G11C8/10 , G11C11/401 , G11C7/02
CPC分类号： G11C8/10
摘要： A circuit and method are disclosed herein which convert signal values on first and second complementary outputs of a second sense amplifier to a single ended data signal for transmission on a read write drive (RWD) line. The circuit includes first and second followers coupled to the first and second complementary outputs, an inverter coupled to an output of the first follower, and a signal driver responsive to an output of the inverter and the second follower to drive signal levels on said RWD line between a first level representing a first data state and a second level representing a second data state.
摘要翻译：本文公开了一种电路和方法，其将第二读出放大器的第一和第二互补输出上的信号值转换为单端数据信号，以在读写驱动（RWD）线上传输。该电路包括耦合到第一和第二互补输出的第一和第二跟随器，耦合到第一跟随器的输出的反相器和响应于反相器和第二跟随器的输出的信号驱动器，以驱动所述RWD线上的信号电平在表示第一数据状态的第一电平和表示第二数据状态的第二电平之间。

8. 发明授权

US06252431B1 Shared PMOS sense amplifier 失效
标题翻译：共享PMOS读出放大器
公开(公告)号：US06252431B1
公开(公告)日：2001-06-26
申请号：US09636475
申请日：2000-08-10
申请人： Kohji Hosokawa
发明人： Kohji Hosokawa
IPC分类号： G11C706
CPC分类号： G11C11/4091 , G11C7/065
摘要： In a sense amplifier for detecting and amplifying a potential difference between a pair of signal lines (BM(BL), /BM(/BL)), a first pull-down circuit (N20, N21), a pull-up circuit (P10, P11), and a second pull-down circuit (N28, N29) are disposed in the recited order between the pair of signal lines. The pull-up circuit (P10, P11) includes a pair of p-type FETs (P10, P11) which configure a flip-flop, and the sources of the pair of p-type FETs are both connected directly to a first constant-voltage source (Vd).
摘要翻译：在用于检测和放大一对信号线（BM（BL），/ BM（/ BL））之间的电位差的读出放大器，第一下拉电路（N20，N21），上拉电路（P10 ，P11）和第二下拉电路（N28，N29）按照所述顺序设置在一对信号线之间。上拉电路（P10，P11）包括配置触发器的一对p型FET（P10，P11），并且一对p型FET的源极都直接连接到第一恒定电压，电压源（Vd）。

9. 发明授权

US06246630B1 Intra-unit column address increment system for memory 失效
标题翻译：内存单位列地址增量系统
公开(公告)号：US06246630B1
公开(公告)日：2001-06-12
申请号：US09017011
申请日：1998-02-02
申请人： Kohji Hosokawa , Toshiaki Kirihata
发明人： Kohji Hosokawa , Toshiaki Kirihata
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A system and method is disclosed herein for providing column address increment pipelining within a single physically contiguous storage array, such as a left or a right unit of a double unit. Thereby, a multiple bank arrangement is provided within a double unit which permits column address increment pipelining to be performed within each bank thereof.
摘要翻译：本文公开的系统和方法用于在单个物理上连续的存储阵列（诸如双单元的左单位或右单元）内提供列地址增量流水线。因此，在双单元内提供多列布置，其允许在其每个库内执行列地址增量流水线化。

10. 发明授权

US07274612B2 DRAM circuit and its operation method 失效
标题翻译： DRAM电路及其操作方法
公开(公告)号：US07274612B2
公开(公告)日：2007-09-25
申请号：US11263260
申请日：2005-10-31
申请人： Kohji Hosokawa , Yohtaroh Mori
发明人： Kohji Hosokawa , Yohtaroh Mori
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C7/02
摘要： A high-density DRAM in a MTBL method which reduces interference noise between bit lines is provided. Duplication of sense amplifiers (SA) and bit switches (BSW) in a conventional MTBL method is eliminated, and one line of sense amplifiers and bit switches (BSW/SA) is arranged between cell areas. Specifically, arrays are horizontally moved and vertically cumulated so as to reduce the areas. Bit line pairs to be connected are alternately interchanged above and below, every one horizontally aligned sense amplifier (SA) such that there is only one bit line pair connected to each sense amplifier. Bit lines of a bit line pair 11 cross at one place on the way, and from the cross, a space between the bit lines is wider. Further, bit lines of a bit line pair 16 do not cross each other, and a space between the bit lines is wider on the way. In a new MTBL method, both in the bit lines connected to the same sense amplifier and in the bit lines among adjacent bit lines connected to the different sense amplifiers, a space between the bit lines changes (widens or narrows) before and after the cross. Thus, the interference noise between any adjacent bit lines is decreased.
摘要翻译：提供了一种降低位线之间干扰噪声的MTBL方法中的高密度DRAM。消除了常规MTBL方法中的读出放大器（SA）和位开关（BSW）的复制，并且在单元区域之间布置一行读出放大器和位开关（BSW / SA）。具体来说，阵列水平移动并垂直累积，以减少面积。要连接的位线对在每个水平对准的读出放大器（SA）上下交替地交换，使得只有一个位线对连接到每个读出放大器。位线对11的位线在途中的一个地方交叉，并且在十字架之间，位线之间的空间较宽。此外，位线对16的位线不会彼此交叉，并且位线之间的空间在路上更宽。在新的MTBL方法中，在连接到相同读出放大器的位线和连接到不同读出放大器的相邻位线之间的位线中，位线之间的空间在交叉之前和之后变化（变宽或变窄）。因此，任何相邻位线之间的干扰噪声减小。

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