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1. 发明申请

US20050045945A1 Insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管
公开(公告)号：US20050045945A1
公开(公告)日：2005-03-03
申请号：US10839791
申请日：2004-05-05
申请人： Koh Yoshikawa , Katsunori Ueno , Hiroshi Kanemaru
发明人： Koh Yoshikawa , Katsunori Ueno , Hiroshi Kanemaru
IPC分类号： H01L29/78 , H01L21/76 , H01L27/04 , H01L29/417 , H01L29/739 , H01L29/76
CPC分类号： H01L29/41741 , H01L29/7397
摘要： An IGBT having a trench gate structure is disclosed which generates decreased noise at switching and displays superiority in saturation voltage to turn-off loss characteristics (trade-off characteristics). In a part of a region on an emitter side surface interposed between trench gates, a sub well region is provided, which is connected to an emitter electrode through diodes. When the IGBT is in a turned-on state, the diodes are brought into a non-conduction state to isolate the sub well region from the emitter electrode, by which carriers are accumulated. When the IGBT is in a turned-off state, the diodes are brought into a conduction state to electrically connect the sub well region to the emitter electrode, by which carriers are discharged at a high speed. In an early stage of turning-on of the IGBT, capacitance of a portion of the gate facing the sub well region is converted to gate-emitter capacitance to thereby reduce gate-collector capacitance, by which electromagnetic noise at switching is reduced.
摘要翻译：公开了具有沟槽栅极结构的IGBT，其在开关时产生降低的噪声，并且将饱和电压的优越性显示为关断损耗特性（权衡特性）。在介于沟槽栅极之间的发射极侧表面的区域的一部分中，设置有通过二极管连接到发射极的子阱区域。当IGBT处于导通状态时，二极管进入非导通状态，以将子阱区域与发射极隔离，由此累积载流子。当IGBT处于关断状态时，二极管进入导通状态，以将子阱区域电连接到发射极电极，载流子以高速放电。在IGBT的导通的早期阶段，面向子阱区域的栅极的一部分的电容被转换为栅极 - 发射极电容，从而减小栅极 - 集电极电容，由此降低开关中的电磁噪声。

2. 发明授权

US07098488B2 Insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管
公开(公告)号：US07098488B2
公开(公告)日：2006-08-29
申请号：US10839791
申请日：2004-05-05
申请人： Koh Yoshikawa , Katsunori Ueno , Hiroshi Kanemaru
发明人： Koh Yoshikawa , Katsunori Ueno , Hiroshi Kanemaru
IPC分类号： H01L29/73
CPC分类号： H01L29/41741 , H01L29/7397
摘要： An IGBT having a trench gate structure is disclosed which generates decreased noise at switching and displays superiority in saturation voltage to turn-off loss characteristics (trade-off characteristics). In a part of a region on an emitter side surface interposed between trench gates, a sub well region is provided, which is connected to an emitter electrode through diodes. When the IGBT is in a turned-on state, the diodes are brought into a non-conduction state to isolate the sub well region from the emitter electrode, by which carriers are accumulated. When the IGBT is in a turned-off state, the diodes are brought into a conduction state to electrically connect the sub well region to the emitter electrode, by which carriers are discharged at a high speed. In an early stage of turning-on of the IGBT, capacitance of a portion of the gate facing the sub well region is converted to gate-emitter capacitance to thereby reduce gate-collector capacitance, by which electromagnetic noise at switching is reduced.
摘要翻译：公开了具有沟槽栅极结构的IGBT，其在开关时产生降低的噪声，并且将饱和电压的优越性显示为关断损耗特性（权衡特性）。在介于沟槽栅极之间的发射极侧表面的区域的一部分中，设置有通过二极管连接到发射极的子阱区域。当IGBT处于导通状态时，二极管进入非导通状态，以将子阱区域与发射极隔离，由此累积载流子。当IGBT处于关断状态时，二极管进入导通状态，以将子阱区域电连接到发射极电极，载流子以高速放电。在IGBT的导通的早期阶段，面向子阱区域的栅极的一部分的电容被转换为栅极 - 发射极电容，从而减小栅极 - 集电极电容，由此降低开关中的电磁噪声。

3. 发明授权

US09466711B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09466711B2
公开(公告)日：2016-10-11
申请号：US12865330
申请日：2009-01-28
申请人： Seiji Momota , Hitoshi Abe , Takashi Shiigi , Takeshi Fujii , Koh Yoshikawa , Tetsutaro Imagawa , Masaki Koyama , Makoto Asai
发明人： Seiji Momota , Hitoshi Abe , Takashi Shiigi , Takeshi Fujii , Koh Yoshikawa , Tetsutaro Imagawa , Masaki Koyama , Makoto Asai
IPC分类号： H01L29/78 , H01L29/96 , H01L29/739 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L27/0629 , H01L27/0658 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/7395 , H01L29/7397 , H01L29/7815 , H01L29/7827
摘要： Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
摘要翻译：在主装置（24）的源电极（25）和电流检测装置（21）的电流检测电极（22）之间连接用于检测电流的电阻器。栅极绝缘体（36）的介电耐受电压大于电阻器和流过电流检测装置（21）的反向偏压的最大电流的乘积。主装置（24）的p体区域（32）的扩散长度短于电流检测装置（21）的p体（31）的扩散长度。主装置（24）的p体区域（32）的端部的曲率半径比电流检测装置（21）的p体（31）的曲率半径小。结果，在逆偏压下，主装置（24）的p体区域（32）的端部的电场变得比电流检测装置的p体区域（31）的电场强 21）。因此，主装置24中的雪崩击穿比电流检测装置（21）更容易发生。

4. 发明授权

US08334581B2 Semiconductor device exhibiting withstand voltages in the forward and reverse directions 有权
标题翻译：在正向和反向方向表现出耐受电压的半导体器件
公开(公告)号：US08334581B2
公开(公告)日：2012-12-18
申请号：US12975650
申请日：2010-12-22
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404
摘要： A semiconductor device according to embodiments of the invention includes an n−-type drift region; a p-type base region formed selectively in the surface portion of the drift region; an n+-type emitter region and a p+-type body region, both formed selectively in the surface portion of base region; and an n-type shell region between the drift region and the base region, a shell region surrounding the entire region below base region. The shell region is doped more heavily than the drift region. The shell region contains an n-type impurity at an effective impurity amount of 8.0×1011 cm −2 or smaller. A drift region exhibits a resistivity low enough to prevent the depletion layer expanding from collector region, formed on the back surface of the drift region, toward a shell region from reaching the shell region.
摘要翻译：根据本发明的实施例的半导体器件包括n型漂移区; 选择性地形成在漂移区域的表面部分中的p型基极区域; n +型发射极区域和p +型体区域，均选择性地形成在基极区域的表面部分中; 以及漂移区域和基极区域之间的n型壳体区域，围绕在基底区域下方的整个区域的壳体区域。壳体区域比漂移区域更重掺杂。外壳区域包含有效杂质量为8.0×10 11 cm -2以下的n型杂质。漂移区域具有足够低的电阻率，以防止耗尽层从形成在漂移区域的背面上的集电极区域朝向壳体区域到达壳体区域扩展。

5. 发明申请

US20110220962A1 SEMICONDUCTOR DEVICE HAVING INSULATED GATE SEMICONDUCTOR ELEMENT, AND INSULATED GATE BIPOLAR TRANSISTOR 有权
标题翻译：具有绝缘栅半导体元件和绝缘栅双极晶体管的半导体器件
公开(公告)号：US20110220962A1
公开(公告)日：2011-09-15
申请号：US13115137
申请日：2011-05-25
申请人： Masaki Koyama , Yoshifumi Okabe , Makoto Asai , Takeshi Fujii , Koh Yoshikawa
发明人： Masaki Koyama , Yoshifumi Okabe , Makoto Asai , Takeshi Fujii , Koh Yoshikawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66348 , H01L29/7397
摘要： A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.
摘要翻译：具有IGBT的半导体器件包括：基板; 衬底上的漂移层和基底层; 穿过基层的沟槽将基层分成基部; 一个基部的发射极区域; 沟槽中的栅极元件; 发射极; 和集电极。一个基座部分提供通道层，而另一个基座部件提供没有发射极区域的浮动层。栅极元件包括靠近沟道层的栅极电极和与浮置层相邻的伪栅极电极。浮子层包括与沟道层相邻的第一浮动层和与沟道层分开的第二浮体层。虚拟栅电极和第一浮动层与基层上的第一浮动布线耦合。虚拟栅电极与第二浮动层隔离。

6. 发明授权

US07943991B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07943991B2
公开(公告)日：2011-05-17
申请号：US11614515
申请日：2006-12-21
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0865 , H01L29/1095 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions. The bottom of each trench is over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.
摘要翻译：公开了一种半导体器件，其包括n型半导体衬底; 在半导体衬底上的交替导电型层，交替导电型层包括交替布置的n型漂移区和p型隔离区; 交替导电型层上的p型沟道区; 以及从p型沟道区的表面形成到各个n型漂移区的沟槽。每个沟槽的底部在p型分隔区域和n型漂移区域之间的pn结上方。半导体器件有助于防止导通电阻增加，获得更高的击穿电压，并减少其特性引起的变化。

7. 发明授权

US07737490B2 Vertical and trench type insulated gate MOS semiconductor device 有权
标题翻译：垂直和沟槽型绝缘栅MOS半导体器件
公开(公告)号：US07737490B2
公开(公告)日：2010-06-15
申请号：US11741015
申请日：2007-04-27
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

8. 发明授权

US07276778B2 Semiconductor system functioning as thyristor in on-state, and as bipolar transistor in transient state or with overcurrent 有权
标题翻译：半导体系统作为晶闸管处于导通状态，并且作为双极晶体管处于瞬态或过电流
公开(公告)号：US07276778B2
公开(公告)日：2007-10-02
申请号：US11170064
申请日：2005-06-30
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7404 , H01L27/0629 , H01L29/7397 , H01L29/87 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/49111 , H01L2224/49175 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate. The self arc-extinguishing device is connected to the IGBT between the emitter electrode and the first terminal. The rectifying device is connected between the first well electrode and the first terminal.
摘要翻译：半导体系统包括自熄灭装置，以及当连接到第二阱电极的第一端子和第二端子之间的电流小时用作晶闸管的IGBT，当该电流较大时，作为双极型晶体管，并根据电流的大小自动在它们之间切换。 IGBT由第一导电型半导体基板形成。在基板的表面层上是与第一阱电极连接的第二导电型阱区。连接发射电极的第一导电型发射极区域设置在阱区的表面层上。控制电极通过部分地覆盖阱和发射极区域的绝缘膜设置。在第二阱电极连接的第二导电型阱层设置在衬底的背面侧。自熄灭装置与发射电极和第一端子之间的IGBT连接。整流装置连接在第一阱电极和第一端子之间。

9. 发明申请

US20070158740A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20070158740A1
公开(公告)日：2007-07-12
申请号：US11564053
申请日：2006-11-28
申请人： Koh Yoshikawa , Akio Sugi , Kouta Takahashi , Manabu Takei , Haruo Nakazawa , Noriyuki Iwamuro
发明人： Koh Yoshikawa , Akio Sugi , Kouta Takahashi , Manabu Takei , Haruo Nakazawa , Noriyuki Iwamuro
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
摘要翻译：公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。形成结层的p型分隔区的杂质浓度比n型漂移区高。这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

10. 发明授权

US08809911B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08809911B2
公开(公告)日：2014-08-19
申请号：US13583666
申请日：2011-10-19
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/66734 , H01L29/7397
摘要： Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.
摘要翻译：多个栅极沟槽形成在n型漂移区域的表面。在栅极沟槽的内壁上的栅氧化膜上形成栅电极。选择性地形成P型基区，以便在相邻栅极沟槽之间的栅极沟槽纵向方向上彼此相邻。 n型发射极区域形成为与p型基极区域的表面层中的栅极沟槽接触。此外，在p型基极区域的表面层中形成浓度高于p型基极区域的p型接触区域，以与n型基极区域的栅极沟道侧接触发射区。 n型发射极区域的栅极沟槽侧的边缘部分终止在p型接触区域的内部。

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