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1. 发明授权

US06820325B2 Integrated air flow control for a pick and place spindle assembly 有权
标题翻译：用于拾取和放置主轴总成的集成气流控制
公开(公告)号：US06820325B2
公开(公告)日：2004-11-23
申请号：US10271761
申请日：2002-10-17
申请人： Koenraad Alexander Gieskes , Michael D. Snyder , John E. Danek
发明人： Koenraad Alexander Gieskes , Michael D. Snyder , John E. Danek
IPC分类号： B23P1900
CPC分类号： H05K13/0409 , Y10S29/044 , Y10T29/5313 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , Y10T29/53191 , Y10T409/309464
摘要： A spindle assembly for a component pick and place machine includes a housing containing a spindle for movement therein along a longitudinal axis of the spindle; the housing accommodating a valve for controlling the flow of air to an inner bore of the spindle; the inner bore of the spindle having an opening at one end for communicating the flow of air for picking and placing the components; and the flow of air from the valve to the inner bore of the spindle is internal to the housing through passageways.
摘要翻译：用于部件拾取和放置机器的主轴组件包括：壳体，其包含用于沿主轴的纵向轴线在其中移动的主轴; 所述壳体容纳用于控制到所述心轴的内孔的空气流的阀; 主轴的内孔在一端具有开口，用于连通用于拾取和放置部件的空气流; 并且从阀的空气到主轴的内孔的流动通过通道在壳体的内部。

2. 发明授权

US09395983B2 Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权
标题翻译：调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作
公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F11/36
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译：为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。

3. 发明授权

US08531899B2 Methods for testing a memory embedded in an integrated circuit 有权
标题翻译：测试嵌入在集成电路中的存储器的方法
公开(公告)号：US08531899B2
公开(公告)日：2013-09-10
申请号：US13613630
申请日：2012-09-13
申请人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译：存储器系统具有包括冗余列的存储器单元阵列的第一存储器。冗余列代替数组中的第一列。第一列包括测试存储单元。阵列接收电源电压。测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。这对于对应用于阵列的电源电压的值做出决定是有用的。

4. 发明授权

US08380779B2 Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand 有权
标题翻译：用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术
公开(公告)号：US08380779B2
公开(公告)日：2013-02-19
申请号：US12474451
申请日：2009-05-29
申请人： Klas M. Bruce , Michael D. Snyder , Ravindraraj Ramaraju , David R. Bearden
发明人： Klas M. Bruce , Michael D. Snyder , Ravindraraj Ramaraju , David R. Bearden
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译：系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。通过参考以下描述和附图可以更好地理解这一点。

5. 发明授权

US08379466B2 Integrated circuit having an embedded memory and method for testing the memory 有权
标题翻译：具有嵌入式存储器的集成电路和用于测试存储器的方法
公开(公告)号：US08379466B2
公开(公告)日：2013-02-19
申请号：US12414758
申请日：2009-03-31
申请人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译：存储器系统具有包括冗余列的存储器单元阵列的第一存储器。冗余列替代数组中的第一列。第一列包括测试存储单元。阵列接收电源电压。测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。这对于对应用于阵列的电源电压的值做出决定是有用的。

6. 发明授权

US08199547B2 Error detection in a content addressable memory (CAM) 有权
标题翻译：内容可寻址存储器（CAM）中的错误检测
公开(公告)号：US08199547B2
公开(公告)日：2012-06-12
申请号：US12703528
申请日：2010-02-10
申请人： Ravindraraj Ramaraju , Michael D. Snyder
发明人： Ravindraraj Ramaraju , Michael D. Snyder
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F11/1064 , G11C29/52
摘要： A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
摘要翻译：内容可寻址存储器和操作方法使用具有多行存储的内容可寻址存储器数据的存储器阵列和用于将接收到的比较数据与存储的内容可寻址存储器数据进行比较的比较电路。为每行提供命中信号和一个或多个奇偶校验位。耦合到每行的存储器阵列的错误的命中检测电路响应于比较数据的奇偶性与与命中信号相关联的行的奇偶校验之间的比较，产生行错误指示，如通过断言该命中信号的命中信号行。错误的命中检测电路使用每一行的行错误指示符来提供指示至少一个被断言的命中信号是否对应于错误命中的输出。

7. 发明授权

US08122437B2 Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors 有权
标题翻译：跟踪和关联无序处理器的数据跟踪和指令跟踪的方法和装置
公开(公告)号：US08122437B2
公开(公告)日：2012-02-21
申请号：US12058874
申请日：2008-03-31
申请人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
发明人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/3636
摘要： In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.
摘要翻译：在数据处理系统中，使用标记位来标识整个流水线中的数据访问指令，以指示该指令满足用户指定的标准（例如，满足感兴趣的数据地址范围）。基于标记位，产生一个顺序程序相关消息，指示何时相对于指令流发生数据访问指令。标记位还用于生成按顺序数据跟踪消息。因此，仅包括满足用户指定标准的数据访问指令的跟踪流可以被后处理并且精确地相关联。

8. 发明申请

US20090172361A1 COMPLETION CONTINUE ON THREAD SWITCH MECHANISM FOR A MICROPROCESSOR 有权
标题翻译：麦克风螺纹开关机构的完成继续
公开(公告)号：US20090172361A1
公开(公告)日：2009-07-02
申请号：US11967430
申请日：2007-12-31
申请人： David C. Holloway , Michael D. Snyder , Suresh Venkumahanti
发明人： David C. Holloway , Michael D. Snyder , Suresh Venkumahanti
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
摘要翻译：公开了一种用于微处理器的线程切换机制和技术，其中完成了第一线程的处理，并且在完成第一线程期间开始了第二线程的延续。在一种形式中，该技术包括处理处理设备的流水线处的第一线程，以及响应于上下文切换事件的发生，在流水线的前端开始处理第二线程。该技术还可以包括响应于上下文切换事件发起指令进展度量。该技术还可以包括在上下文切换事件发生时能够完成在流水线的后端处理第一线程的指令，直到指令进度度量的到期为止。

9. 发明申请

US20090103379A1 INTEGRATED CIRCUIT MEMORY HAVING DYNAMICALLY ADJUSTABLE READ MARGIN AND METHOD THEREFOR 有权
标题翻译：具有动态可调整性的集成电路存储器及其方法
公开(公告)号：US20090103379A1
公开(公告)日：2009-04-23
申请号：US11875997
申请日：2007-10-22
申请人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
发明人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/02 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/0409
摘要： A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.
摘要翻译：提供了一种用于在包括多个可寻址单元的集成电路中在操作期间动态地控制存储器的读出放大器差分裕度的方法。该方法包括将与多个可寻址单元相对应的读出放大器差分裕度设置为第一值。该方法还包括如果当从多个可寻址单元的集合读取数据时发生读取数据错误，则将与多个可寻址单元相对应的读出放大器差分裕度设置为第二值，其中第二值大于第一个值。

10. 发明申请

US20080082843A1 DYNAMIC BRANCH PREDICTION PREDICTOR 有权
标题翻译：动态分支预测预测
公开(公告)号：US20080082843A1
公开(公告)日：2008-04-03
申请号：US11536173
申请日：2006-09-28
申请人： Sergio Schuler , Michael D. Snyder , Leick D. Robinson , David M. Thompson
发明人： Sergio Schuler , Michael D. Snyder , Leick D. Robinson , David M. Thompson
IPC分类号： G06F15/00
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
摘要翻译：处理器具有取出单元和分支执行单元。提取单元具有分支预测器。分支预测器具有分支目标缓冲器和分支方向预测器。唤醒值是预取在分支获取之后执行的指令提取的数量。因此，对于第一分支，例如，预测第一尾数。分支预测器的低功率模式响应于其中命中响应于第一分支的分支目标缓冲器中的命中而启用第一唤醒值的持续时间。

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