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1. 发明授权

US07681021B2 Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch 有权
标题翻译：使用唤醒值进行动态分支预测，以使得能够在分支和后续分支之间的预测指令取数的低功率模式
公开(公告)号：US07681021B2
公开(公告)日：2010-03-16
申请号：US11536173
申请日：2006-09-28
申请人： Sergio Schuler , Michael D. Snyder , Leick D. Robinson , David M. Thompson
发明人： Sergio Schuler , Michael D. Snyder , Leick D. Robinson , David M. Thompson
IPC分类号： G06F9/00 , G06F1/32
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
摘要翻译：处理器具有取出单元和分支执行单元。提取单元具有分支预测器。分支预测器具有分支目标缓冲器和分支方向预测器。唤醒值是预取在分支获取之后执行的指令提取的数量。因此，对于第一分支，例如，预测第一尾数。分支预测器的低功率模式响应于其中命中响应于第一分支的分支目标缓冲器中的命中而启用第一唤醒值的持续时间。

2. 发明申请

US20080082843A1 DYNAMIC BRANCH PREDICTION PREDICTOR 有权
标题翻译：动态分支预测预测
公开(公告)号：US20080082843A1
公开(公告)日：2008-04-03
申请号：US11536173
申请日：2006-09-28
申请人： Sergio Schuler , Michael D. Snyder , Leick D. Robinson , David M. Thompson
发明人： Sergio Schuler , Michael D. Snyder , Leick D. Robinson , David M. Thompson
IPC分类号： G06F15/00
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
摘要翻译：处理器具有取出单元和分支执行单元。提取单元具有分支预测器。分支预测器具有分支目标缓冲器和分支方向预测器。唤醒值是预取在分支获取之后执行的指令提取的数量。因此，对于第一分支，例如，预测第一尾数。分支预测器的低功率模式响应于其中命中响应于第一分支的分支目标缓冲器中的命中而启用第一唤醒值的持续时间。

3. 发明授权

US08904150B2 Microprocessor systems and methods for handling instructions with multiple dependencies 有权
标题翻译：用于处理具有多个依赖关系的指令的微处理器系统和方法
公开(公告)号：US08904150B2
公开(公告)日：2014-12-02
申请号：US13116325
申请日：2011-05-26
申请人： Thang M. Tran , Leick D. Robinson
发明人： Thang M. Tran , Leick D. Robinson
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3836 , G06F9/3838
摘要： A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues.
摘要翻译：处理器包括提供由处理器执行的指令的指令单元，对从指令单元接收的指令进行解码并发出指令的解码/发布单元以及耦合到解码/发布单元的多个执行队列。来自解码/发布单元的每个发出的指令被存储到多个执行队列中的至少一个队列的条目中，其中多个执行队列中的每个条目被配置为存储发出的指令和与发出的执行队列对应的重复指示符指示所发出的指令的重复指令是否也存储在多个执行队列的另一个队列的条目中。

4. 发明授权

US08359346B2 Hash function for hardware implementations 有权
标题翻译：硬件实现的哈希功能
公开(公告)号：US08359346B2
公开(公告)日：2013-01-22
申请号：US12612757
申请日：2009-11-05
申请人： Brian C. Grayson , Leick D. Robinson , Benjamin M. Menchaca
发明人： Brian C. Grayson , Leick D. Robinson , Benjamin M. Menchaca
IPC分类号： G06F7/00
CPC分类号： H04L63/10 , H04L9/0643 , H04L2209/12 , H04L2209/80
摘要： A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.
摘要翻译：呈现出使用最小逻辑产生雪崩标准散列值的逻辑块。逻辑块包括第一异或函数，第二异或函数和OR函数。第一个异或功能从数据包接收两个输入位，并且基于两个输入位之间的独占分离产生线性输出值。 OR功能从数据包接收两个不同的输入位，并且基于两个不同输入位之间的逻辑分离产生第一非线性输出值。第二异或功能接收线性输出值和第一非线性输出值，并且基于线性输出值和第一非线性输出值之间的排除分离产生第二非线性输出值。反过来，第二非线性输出值用于产生数据包的散列值。

5. 发明申请

US20110106866A1 Hash Function for Hardware Implementations 有权
标题翻译：硬件实现的哈希功能
公开(公告)号：US20110106866A1
公开(公告)日：2011-05-05
申请号：US12612757
申请日：2009-11-05
申请人： Brian C. Grayson , Leick D. Robinson , Benjamin M. Menchaca
发明人： Brian C. Grayson , Leick D. Robinson , Benjamin M. Menchaca
IPC分类号： G06F7/00
CPC分类号： H04L63/10 , H04L9/0643 , H04L2209/12 , H04L2209/80
摘要： A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.
摘要翻译：呈现出使用最小逻辑产生雪崩标准散列值的逻辑块。逻辑块包括第一异或函数，第二异或函数和OR函数。第一个异或功能从数据包接收两个输入位，并且基于两个输入位之间的独占分离产生线性输出值。 OR功能从数据包接收两个不同的输入位，并且基于两个不同输入位之间的逻辑分离产生第一非线性输出值。第二异或功能接收线性输出值和第一非线性输出值，并且基于线性输出值和第一非线性输出值之间的排除分离产生第二非线性输出值。反过来，第二非线性输出值用于产生数据包的散列值。

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